US-12625785-B2 - Persistent data structure to track and manage SSD defects

Abstract

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

Inventors

• Naveen Vittal Prabhu
• Aliasgar Madraswala
• Rohit Shenoy
• Shankar Natarajan
• Arun S. Athreya

Assignees

• Intel NDTM US LLC

Dates

Publication Date

20260512

Application Date

20240702

Claims (20)

1. 1 . An electronic apparatus, comprising: one or more substrates; and logic coupled to the one or more substrates, the logic to: control access to a persistent storage media including a memory block based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for the memory block, determine that the data structure indicates at least one sub-block for the memory block having a read fail, program the at least one sub-block for the memory block, and read the data structure from the persistent storage media, including issuing an unlock command, a read command, and at least one of a reset command and an exit command.
2. 2 . The electronic apparatus of claim 1 , wherein the logic is further to update the data structure in response to the read fail on the memory block to indicate that the at least one sub-block corresponds to the read fail.
3. 3 . The electronic apparatus of claim 2 , wherein the logic is further to move an affected sub-block contents to another block in response to the read fail on the block.
4. 4 . The electronic apparatus of claim 1 , wherein the data structure comprises a bitmap structure.
5. 5 . The electronic apparatus of claim 4 , wherein the logic to store the data structure comprises logic to store the bitmap structure in a one-time-programmable portion of the persistent storage media.
6. 6 . The electronic apparatus of claim 1 , wherein the persistent storage media comprises one or more of NAND-based media and 3D crosspoint media.
7. 7 . A method of controlling storage, comprising: controlling access to a persistent storage media including a memory block based on a block and sub-block access structure, storing a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for the memory block, determining that the data structure indicates at least one sub-block for the memory block having a read fail, programming the at least one sub-block for the memory block, and reading the data structure from the persistent storage media, including issuing an unlock command, a read command, and at least one of a reset command and an exit command.
8. 8 . An electronic storage system, comprising: persistent storage media; a controller to control access to the persistent storage media including a memory block based on a block and sub-block access structure; and logic communicatively coupled to the controller and the persistent storage media, the logic to: store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for the memory block, determine that the data structure indicates at least one sub-block for the memory block having a read fail, program the at least one sub-block for the memory block, and read the data structure from the persistent storage media, including issuing an unlock command, a read command, and at least one of a reset command and an exit command.
9. 9 . The electronic storage system of claim 8 , wherein the logic is further to update the data structure in response to the read fail on the memory block to indicate that the at least one sub-block corresponds to the read fail.
10. 10 . The electronic storage system of claim 9 , wherein the logic is further to move an affected sub-block contents to another block in response to the read fail on the block.
11. 11 . The electronic storage system of claim 8 , wherein the data structure comprises a bitmap structure.
12. 12 . The electronic storage system of claim 11 , wherein the logic to store the data structure comprises logic to store the bitmap structure in a one-time-programmable portion of the persistent storage media.
13. 13 . The electronic storage system of claim 8 , wherein the persistent storage media comprises one or more of NAND-based media and 3D crosspoint media.
14. 14 . The method of claim 7 , wherein the persistent storage media comprises one or more of NAND-based media and 3D crosspoint media.
15. 15 . The method of claim 7 , further comprising updating the data structure in response to the read fail on the memory block to indicate that the at least one sub-block corresponds to the read fail.
16. 16 . The method of claim 15 , further comprising moving an affected sub-block contents to another block in response to the read fail on the block.
17. 17 . The method of claim 7 , wherein the data structure comprises a bitmap structure.
18. 18 . The method of claim 17 , wherein storing the data structure comprises storing the bitmap structure in a one-time-programmable portion of the persistent storage media.
19. 19 . The method of claim 7 , wherein in accordance with a determination that the data structure indicates the at least one sub-block for the memory block having the read fail, the at least one sub-block for the memory block is programmed with dummy data.
20. 20 . The electronic apparatus of claim 1 , wherein the logic is configured to: in response to a request to erase the block, determine that the data structure indicates the at least one sub-block for the memory block having the read fail; and in response to a power interruption, read the data structure from the persistent storage media.

Description

CLAIM OF PRIORITY This application is a continuation of, and claims priority to, U.S. patent application Ser. No. 17/133,834, filed on Dec. 24, 2020 and titled “PERSISTENT DATA STRUCTURE TO TRACK AND MANAGE SSD DEFECTS,” which is incorporated by reference herein in its entirety. BACKGROUND NAND flash devices includes a variety of different types NAND-based media with different sets of characteristics. Single-level cell (SLC) NAND stores one bit in each cell, multi-level cell (MLC) NAND stores two bits in each cell, triple-level cell (TLC) NAND stores three bits in each cell, and quad-level cell (QLC) NAND stores four bits in each cell. In general terms, as the number of bits per cell increases, the endurance, performance, and expense generally decrease while the capacity increases. A solid state drive (SSD) may have a variety of specifications including performance specifications, thermal specifications, and reliability/endurance specifications. The Nonvolatile Memory (NVM) Express (NVMe) specification (nvmexpress.org) describes various features and specifications related to access to a storage device such as a NAND-based SSD. BRIEF DESCRIPTION OF THE DRAWINGS The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures: FIG. 1 is a block diagram of an example of an electronic storage system according to an embodiment; FIG. 2 is a block diagram of an example of an electronic apparatus according to an embodiment; FIGS. 3A to 3B are flowcharts of an example of a method of controlling storage according to an embodiment; FIG. 4 is a block diagram of an example of a solid state drive (SSD) device according to an embodiment; FIG. 5 is a flowchart of another example of a method of controlling storage according to an embodiment; FIG. 6 is a flowchart of another example of a method of controlling storage according to an embodiment; FIG. 7 is a flowchart of another example of a method of controlling storage according to an embodiment; FIG. 8 is a flowchart of another example of a method of controlling storage according to an embodiment; FIG. 9 is a block diagram of an example of a computing system according to an embodiment; and FIG. 10 is a block diagram of an example of a solid state drive (SSD) device according to an embodiment. DETAILED DESCRIPTION One or more embodiments or implementations are now described with reference to the enclosed figures. While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may also be employed in a variety of other systems and applications other than what is described herein. While the following description sets forth various implementations that may be manifested in architectures such as system-on-a-chip (SoC) architectures for example, implementation of the techniques and/or arrangements described herein are not restricted to particular architectures and/or computing systems and may be implemented by any architecture and/or computing system for similar purposes. For instance, various architectures employing, for example, multiple integrated circuit (IC) chips and/or packages, and/or various computing devices and/or consumer electronic (CE) devices such as set top boxes, smartphones, etc., may implement the techniques and/or arrangements described herein. Further, while the following description may set forth numerous specific details such as logic implementations, types and interrelationships of system components, logic partitioning/integration choices, etc., claimed subject matter may be practiced without such specific details. In other instances, some material such as, for example, control structures and full software instruction sequences, may not be shown in detail in order not to obscure the material disclosed herein. The material disclosed herein may be implemented in hardware, Field Programmable Gate Array (FPGA), firmware, driver, software, or any combination thereof. The material disclosed herein may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by Moore Machine, Mealy Machine, and/or one or more processors. A machine-readable medium may include any medium and/or mechanism for storing or transmitting information in a form readable