US-12625786-B2 - Memory systems, operation methods thereof, and computer-readable storage mediums to detect an abnormality in firmware

US12625786B2US 12625786 B2US12625786 B2US 12625786B2US-12625786-B2

Abstract

The present disclosure provides a memory system, an operation method thereof, and a computer-readable storage medium. The memory system includes: a memory device and a memory controller coupled with the memory device. The memory system includes a general-purpose input/output interface including a first pin that is configurable to receive data transmitted by serial communication. The memory controller is configured to: trigger an interruption by the first pin in response to abnormality of a firmware of the memory system during operation; and trigger an assert dump mode in response to the interruption triggered by the first pin.

Inventors

Zhebo Wu

Assignees

YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240523
Priority Date: 20240321

Claims (20)

1 . A memory system, comprising a memory device and a memory controller coupled with the memory device, and the memory system further including a general-purpose input/output interface, wherein the general-purpose input/output interface includes a first pin that is configurable to receive data transmitted by serial communication, and the memory controller is configured to: detect a change in a signal level of the first pin, wherein to detect the change in the signal level the first pin is configured to a first mode: trigger an interruption by the first pin in response to an abnormality of a firmware of the memory system during operation, wherein the interruption is triggered in response to the signal level of the first pin satisfying a threshold and causing the first pin to switch from the first mode to trigger the interruption; and trigger an assert dump mode in response to the interruption triggered by the first pin, wherein, after triggering the assert dump mode, the first pin is configured to a second mode to receive the data transmitted by serial communication.
2 . The memory system of claim 1 , wherein the memory controller is further configured to: configure the first pin into the first mode before triggering the interruption by the first pin, wherein, in the first mode, the first pin is configurable to receive the signal level; and trigger the interruption when the signal level received by the first pin is in a first state in response to the first pin being in the first mode.
3 . The memory system of claim 2 , wherein the first state includes a rising edge state, a falling edge state, a high level state, or a low level state.
4 . The memory system of claim 3 , further including a first grounding pin, wherein the memory controller is configured to: put the signal level received by the first pin into the rising edge state in response to the first pin being short-circuited with the first grounding pin; and trigger the interruption in response to the signal level received by the first pin being in the rising edge state.
5 . The memory system of claim 4 , further including a second pin and a second grounding pin, wherein the second pin is configured to select a program start-up method when the memory system is powered on, and the memory controller is further configured to: put the signal level received by the second pin into the rising edge state in response to the second pin being short-circuited with the second grounding pin; and trigger the interruption in response to the signal level received by the first pin being in the rising edge state and the signal level received by the second pin being in the rising edge state.
6 . The memory system of claim 2 , wherein the memory controller is configured to configure the first pin into the first mode at a user usage stage.
7 . The memory system of claim 2 , further including a PCI Express interface, wherein the memory controller is configured to, at a debug stage of the memory system, configure the first pin into the first mode in response to an abnormality of the PCI Express interface and the abnormality of the firmware of the memory system during operation.
8 . The memory system of claim 7 , wherein the memory controller is further configured to perform assert dump processing in response to triggering the assert dump mode, wherein the assert dump processing includes saving abnormal state information into the memory device.
9 . The memory system of claim 8 , wherein the memory controller is further configured to: at the debug stage of the memory system, disable the interruption in response to completing the assert dump processing; and configure the first pin into the second mode in response to that the interruption is disabled.
10 . The memory system of claim 9 , wherein the memory controller is further configured to send, by the PCI Express interface, the abnormal state information to a host coupled with the memory system after the memory system is repowered on, in response to the interruption being disabled.
11 . The memory system of claim 1 , including a memory card, a solid state drive, or a universal flash memory.
12 . An operation method of a memory system, comprising: detecting a change in a signal level of a first pin of a general-purpose input/output interface of the memory system that is configurable to receive data transmitted by serial communication, wherein to detect the change in the signal level the first pin is configured to a first mode; triggering an interruption by the first pin in response to an abnormality of a firmware of the memory system during operation, wherein the interruption is triggered in response to the signal level of the first pin satisfying a threshold and causing the first pin to switch from the first mode to trigger the interruption; and triggering an assert dump mode in response to the interruption triggered by the first pin, wherein, after triggering the assert dump mode, the first pin is configured to a second mode to receive the data transmitted by serial communication.
13 . The operation method of claim 12 , further including: configuring the first pin into the first mode before triggering the interruption by the first pin, wherein, in the first mode, the first pin is configurable to receive the signal level; and triggering the interruption by the first pin when the signal level received by the first pin is in a first state in response to the first pin being in the first mode.
14 . The operation method of claim 13 , wherein the first state includes a rising edge state, a falling edge state, a high level state, or a low level state.
15 . The operation method of claim 14 , wherein the memory system further includes a first grounding pin, and triggering the interruption when the signal level received by the first pin is in the first state in response to the first pin being in the first mode includes: putting the signal level received by the first pin into the rising edge state in response to the first pin being short-circuited with the first grounding pin; and triggering the interruption in response to the signal level received by the first pin being in the rising edge state.
16 . The operation method of claim 15 , wherein the memory system further includes a second pin and a second grounding pin, wherein the second pin is configured to select a program start-up method when the memory system is powered on, and triggering the interruption when the signal level received by the first pin is in the first state in response to the first pin being in the first mode further includes: putting the signal level received by the second pin into the rising edge state in response to the second pin being short-circuited with the second grounding pin; and triggering the interruption in response to the signal level received by the first pin being in the rising edge state and the signal level received by the second pin being in the rising edge state.
17 . The operation method of claim 13 , wherein configuring the first pin into the first mode includes configuring the first pin into the first mode at a user usage stage.
18 . The operation method of claim 13 , wherein the memory system further includes a PCI Express interface, and configuring the first pin into the first mode includes, at a debug stage of the memory system, configuring the first pin into the first mode in response to an abnormality of the PCI Express interface and the abnormality of the firmware of the memory system during operation.
19 . The operation method of claim 18 , further including performing assert dump processing in response to triggering the assert dump mode, wherein the assert dump processing includes saving abnormal state information into a memory device.
20 . The operation method of claim 19 , further including: at the debug stage of the memory system, disabling the interruption in response to completing the assert dump processing; and configuring the first pin into the second mode in response to the interruption being disabled.

Description

REFERENCE TO RELATED APPLICATION The present application claims the benefit of priority to China Application No. 202410330634.7, filed on Mar. 21, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the field of semiconductor technology, and particularly to memory systems, operation methods thereof, and computer-readable storage mediums. BACKGROUND With the rapid development of data storage technology, more and more data memory systems have been present in electronic apparatuses used by people, such as Solid State Drives (SSDs), etc. The SSDs have been widely applied in military, vehicle, industrial, medical, and aviation fields, etc. due to the characteristics of high read-write speeds, anti-vibration, low power consumption, noiselessness, low heat, light weight, and the like. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of an example system having a memory system provided by examples of the present disclosure. FIG. 2 is a schematic diagram of an example memory card having a memory system provided by examples of the present disclosure. FIG. 3 is a schematic diagram of an example solid state drive having a memory system provided by examples of the present disclosure. FIG. 4 is a schematic diagram of an example memory device comprising a peripheral circuit provided by examples of the present disclosure. FIG. 5 is a schematic cross-sectional view of a memory array comprising a memory cell string provided by examples of the present disclosure. FIG. 6 is a schematic diagram of an example memory device comprising a memory array and a peripheral circuit provided by examples of the present disclosure. FIG. 7 is a flow diagram I of an operation method of a memory system provided by examples of the present disclosure. FIG. 8 is a schematic structural diagram I of a memory system provided by examples of the present disclosure. FIG. 9 is a schematic structural diagram II of a memory system provided by examples of the present disclosure. FIG. 10 is a flow diagram II of an operation method of a memory system provided by examples of the present disclosure. FIG. 11 is a flow diagram III of an operation method of a memory system provided by examples of the present disclosure. FIG. 12 is a flow diagram IV of an operation method of a memory system provided by examples of the present disclosure. DETAILED DESCRIPTION Example implementations disclosed by the present disclosure will be described below in more details with reference to the drawings. Although the example implementations of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be implemented in various forms and should not be limited by the specific implementations set forth herein. Rather, these implementations are provided for a more thorough understanding of the present disclosure, and to fully convey a scope disclosed by the present disclosure to those skilled in the art. In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. However, it is apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features well-known in the field are not described. That is, not all the features of the actual examples are described herein, and well-known functions and structures are not described in detail. In the drawings, like reference numerals denote like elements throughout the specification. It is to be understood that, spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “over”, “upper”, and the like, may be used herein for ease of description to describe the relationship between one element or feature and other elements or features as illustrated in the figures. It is to be understood that, the spatially relative terms are intended to further encompass different orientations of a device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the drawings is turned over, then the elements or the features described as “below” or “under” or “beneath” other elements may be oriented “on” the other elements or features. Thus, the example terms “below” and “beneath”, may comprise both upper and lower orientations. The device may be orientated otherwise (rotated by 90 degrees or in other orientations), and the spatially descriptive terms used herein are interpreted accordingly. The terms used herein are only intended to describe the specific examples, and are not used as limitations of the present disclosure. As used herein, unless otherwise indicated expressly in the context, “a”, “an” and “the” in a singular form are also intended to comprise a plural form. It should also be understood that terms “consist of” and/or “comprise”,