US-12625790-B2 - Tracing circuit, semiconductor device, tracer, and tracing system

US12625790B2US 12625790 B2US12625790 B2US 12625790B2US-12625790-B2

Abstract

A tracing circuit is integrated in a semiconductor device along with a microprocessor including an m-bit program counter, and externally outputs a tracing clock along with an n-bit tracing data (where 2≤n≤m). The tracing circuit, when the program counter remains unchanged, synchronously with the tracing clock sets the tracing data to a first output value; when the program counter is incremented, synchronously with the tracing clock sets the tracing data to a second output value; and when the program counter is loaded, synchronously with the tracing clock sets the tracing data to a third output value, and then suspends the state machine in the microprocessor and split-outputs, as the tracing data, the branch destination address or interrupt destination address loaded in the program counter.

Inventors

Takahiro Nishiyama

Assignees

ROHM CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240724
Priority Date: 20191018

Claims (10)

1 . A tracing circuit for use with a microprocessor having an m-bit (where 2≤m) program counter, the tracing circuit externally outputting tracing data synchronously with a tracing clock, the tracing circuit being configured to change an output value of the externally output tracing data according to operation of the program counter, the tracing circuit being configured to include: a status generator configured to generate a status signal that has a first output value when the program counter remains unchanged, has a second output value when the program counter is incremented, and has a third output value when the program counter is loaded; a counter configured to start operating when the status signal turns to the third output value and to stop operating when a split-output period for a branch destination address or interrupt destination address expires; and a selector configured to select the status signal as the tracing data when the counter is not operating and to select part of the branch destination address or interrupt destination address as the tracing data when the counter is operating.
2 . The tracing circuit according to claim 1 , wherein the tracing data is configured to have n bits (where 2≤n≤m).
3 . The tracing circuit according to claim 1 , wherein when the program counter remains unchanged, synchronously with the tracing clock, the tracing data is set to the first output value, when the program counter is incremented, synchronously with the tracing clock, the tracing data is set to the second output value, and when the program counter is loaded, synchronously with the tracing clock, the tracing data is set to the third output value and, with a state machine in the microprocessor temporarily suspended, the branch destination address or interrupt destination address loaded in the program counter is split-output as the tracing data.
4 . A semiconductor device comprising: the tracing circuit according to claim 1 ; and the microprocessor.
5 . The semiconductor device according to claim 4 , wherein the microprocessor is configured to read an instruction code from a program memory by using an output value of the program counter as a read address and to decode and execute the instruction code.
6 . A tracer configured to receive the tracing clock and the tracing data from the semiconductor device according to claim 4 to monitor the tracing data and output a tracing result.
7 . A tracer configured to receive, from a semiconductor device configured to include the tracing circuit according to claim 1 and the microprocessor, the tracing clock and the tracing data to monitor the tracing data and output a tracing result, the tracer comprising: an emulated program counter; a decoder configured, when the tracing data is the first output value, to keep the emulated program counter unchanged, when the tracing data is the second output value, to increment the emulated program counter, and when the tracing data is the third output value, to load the emulated program counter sequentially with the branch destination address or interrupt destination address that is subsequently split-input; a latch configured to acquire as a definitive value an output value of the emulated program counter synchronously with the tracing clock except during a split-input period for the branch destination address or interrupt destination address; and a trace memory configured to store as the tracing result the definitive value that is sequentially acquired by the latch.
8 . A tracing system comprising: the semiconductor device according to claim 4 ; the tracer according to claim 6 ; and a host configured to display, store, and analyze the tracing result.
9 . A tracing method comprising: a first step of, when tracing operation is started, checking whether a program counter has been incremented; a second step of, if the first step yields a negative result, checking whether the program counter has been changed; a third step of, if the second step yields a negative result, setting tracing data to a first output value; a fourth step of, if the first step yields a positive result, setting the tracing data to a second output value; a fifth step of, if the second step yields a positive result, setting the tracing data to a third output value; a sixth step of starting pulse counting operation for a tracing clock by use of a counter and bringing a state machine into a temporarily suspended state; a seventh step of split-outputting, as the tracing data, part of a branch destination address or interrupt destination address synchronously with the tracing clock; an eighth step of checking whether a count value of the counter has reached a predetermined value; and a ninth step of, if the eighth step yields a positive result, resetting the count value of the counter to zero, restoring the state machine from the temporarily suspended state, and returning control to the first step, wherein, if the eighth step yields a negative result, control is returned to the seventh step to repeat a sequence of operation.
10 . A tracing method comprising: a first step of, when tracing operation is started, initializing an output value of an emulated program counter; a second step of checking whether input tracing data is a second output value; a third step of, if the second step yields a negative result, checking whether the input tracing data is a third output value; a fourth step of, if the third step yields a negative result, determining that the input tracing data is a first output value and returning control to the second step; a fifth step of, if the second step yields a positive result, incrementing the emulated program counter and returning control to the second step; a sixth step of, if the third step yields a positive result, storing part of a branch destination address or interrupt destination address, which is split-input as the tracing data, in corresponding bits in the emulated program counter; a seventh step of checking whether all bit values of the branch destination address or interrupt destination address have been stored in the emulated program counter; and an eighth step of, if the seventh step yields a positive result, determining an output value of the emulated program counter as a definitive value of the emulated program counter and returning control to the second step, wherein, if the seventh step yields a negative result, control is returned to the sixth step to continue to split-input the branch destination address or interrupt destination address to repeat a sequence of operation.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation application of U.S. patent application Ser. No. 17/761,713 filed on Mar. 18, 2022, which is a U.S. National Phase application under 35 U.S.C. § 371 of International Patent Application No. PCT/JP2020/039036, filed Oct. 16, 2020, which claims priority to JP Application No. 2019-191068, filed Oct. 18, 2019, the contents of which are hereby incorporated by reference. TECHNICAL FIELD The invention disclosed herein relates to tracing circuits. BACKGROUND ART With an LSI incorporating a microprocessor (such as a CPU [central processing unit] that performs program operation, one often wishes to trace the program operation from outside the LSI, that is, to see how the program runs. The purpose may vary, and can be to find the cause of the program failing to run as intended, or to check the code coverage of a program operation test (to check whether the test covers the entire code). To meet such requirements, it is necessary to see how the CPU reads instruction codes in a program memory, in other words, to trace the read address in the program memory inside the CPU. Examples of conventional technology related to what has been discussed above are seen in Patent Documents 1 and 2 identified below. CITATION LIST Patent Literature Patent Document 1: Japanese Patent registered as No. 2727947, DescriptionPatent Document 2: Japanese Patent registered as No. 3775462, Description SUMMARY OF INVENTION Technical Problem Inconveniently, according to Patent Document 1, a tracing storage means (tracing memory) needs to be provided inside the LSI, or alternatively all address buses need to be output to outside the LSI. According to Patent Document 2, when a branching instruction is executed, only part of the relevant information is output to the outside, and thus deriving a branch destination address requires analysis outside the LSI. Failure to single out one branch destination address from a plurality of candidate ones makes tracing impossible. In view of the above-mentioned problems encountered by the present inventor, an object of the invention disclosed herein is to provide a tracing circuit that allows easy and complete tracing of the read address in a program memory from outside a semiconductor device. Solution to Problem According to one aspect of what is disclosed herein, a tracing circuit is for integration in a semiconductor device along with a microprocessor including an m-bit program counter, and is configured to externally output a tracing clock along with an n-bit tracing data (where 2≤n≤m). The tracing circuit is configured such that, when the program counter remains unchanged, synchronously with the tracing clock, the tracing circuit sets the tracing data to a first output value; when the program counter is incremented, synchronously with the tracing clock, the tracing circuit sets the tracing data to a second output value; and when the program counter is loaded, synchronously with the tracing clock, the tracing circuit sets the tracing data to a third output value, and then suspends the state machine in the microprocessor and split-outputs, as the tracing data, the branch destination address or interrupt destination address loaded in the program counter. (A first configuration.) The tracing circuit of the first configuration described above may include: a status generator configured to generate a status signal that has the first output value when the program counter remains unchanged, has the second output value when the program counter is incremented, and has the third output value when the program counter is loaded; a counter configured to start operating when the status signal turns to the third output value and to stop operating when the split-output period for the branch destination address or interrupt destination address expires; and a selector configured to select the status signal as the tracing data when the counter is not operating and to select part of the branch destination address or interrupt destination address as the tracing data when the counter is operating. (A second configuration.) In the tracing circuit of the second configuration described above, the status generator may be configured to generate the status signal by monitoring an internal control signal in the microprocessor. (A third configuration.) In the tracing circuit of any of the first to third configurations described above, the tracing clock may be the driving clock for the microprocessor. (A fourth configuration.) According to another aspect of what is disclosed herein, a semiconductor device has integrated therein: the tracing circuit according to any of the first to fourth configurations described above; and a microprocessor configured to read an instruction code from a program memory by using the output value of the program counter as a read address and to decode and execute the instruction code. (A fifth configuration.) In the semiconductor device of th