US-12625793-B2 - Tracking debug events from an autonomous module through a data pipeline

Abstract

Devices, streaming engines and functionality are provided for identifying a debug event associated with a data element of a data stream, and performing debugging when a processor executes a software program in connection with the data stream. The debug event is tracked through a data pipeline to the processor. In an embodiment, the debug event is acted on only when the processor is ready to consume the data element associated with the debug event. In an embodiment, the debug event is determined by monitoring iteration counts of loop counters associated with an address generator and comparing the iteration counts to respective stored count values.

Inventors

• Joseph Raymond Michael Zbiciak
• Jason Lynn Peck

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260512

Application Date

20240823

Claims (20)

1. 1 . A streaming engine comprising: an address generator that includes loop counters configured to generate respective iteration counts; and debug event detection circuitry coupled to the address generator, the debug event detection circuitry including: storage configured to store a respective count value and a respective bypass indicator for each of the loop counters; a set of comparators coupled to the storage and the loop counters; and event generation logic coupled to the storage and to the set of comparators, the event generation logic configured to generate a debug event based on current iteration counts generated by the loop counters, the stored count values, and the bypass indicators.
2. 2 . The streaming engine of claim 1 , further comprising: a set of OR logic circuits coupled to the storage and respectively coupled to the set of comparators.
3. 3 . The streaming engine of claim 2 , wherein the event generation logic includes an AND logic circuit coupled to the set of OR logic circuits.
4. 4 . The streaming engine of claim 1 , further comprising: a data buffer configured to store a set of data elements retrieved from a memory based on a set of memory addresses generated by the address generator in response to an instruction, wherein a first data element of the set of data elements is associated with the debug event; and a debug event buffer configured to store the debug event such that the debug event propagates through the debug event buffer as the first data element propagates through the data buffer.
5. 5 . The streaming engine of claim 4 , wherein each of the data buffer and the debug event buffer is structured as a first-in-first-out buffer.
6. 6 . The streaming engine of claim 1 , wherein the storage includes: a loop count memory configured to store the respective count value for each of the loop counters; and a loop bypass memory configured to store the respective bypass indicator for each of the loop counters.
7. 7 . The streaming engine of claim 6 , wherein the set of comparators is configured to: compare a respective current iteration count of a respective loop counter of the loop counters to the corresponding stored count value to generate respective comparison results.
8. 8 . The streaming engine of claim 7 , wherein the event generation logic is configured to: determine whether to generate the debug event based on the comparison results and the bypass indicators.
9. 9 . The streaming engine of claim 7 , wherein: each comparator of the set of comparators is configured to output a result signal indicative of the respective comparator result; and the event generation logic includes a multiplexor coupled to the set of comparators to receive as a select signal one of the result signals, and a register coupled to the multiplexer and configured to provide inputs to the multiplexer.
10. 10 . The streaming engine of claim 9 , wherein the multiplexor is configured as a lookup table, and the register is configured to receive a lookup table code.
11. 11 . The streaming engine of claim 1 , wherein the streaming engine is configured to be coupled to a processor that is configured to process the debug event as one of a breakpoint and a probe point.
12. 12 . A device comprising: a streaming engine configured to: generating a data stream of data elements; generate, using an address generator of the streaming engine, respective addresses for the data elements; generate iteration counts using loop counters of the address generator; retrieve a first data element of the data elements using the address generated by the address generator for the first data element; and determine, for the first data element, whether debug event criteria stored in the streaming engine match a current state of the loop counters.
13. 13 . The device of claim 12 , wherein the streaming engine is further configured to: associate a debug indicator with the first data element when the stored debug event criteria match the current state of the loop counters, propagate the debug indicator along with the first data element, and buffer the first data element and the debug indicator until consumed by a processor to which the data stream is propagated.
14. 14 . The device of claim 13 , wherein the processor is configured to: execute a program including accessing the data stream in response to a program instruction, and determine whether the first data element associated with the debug indicator is in the data stream.
15. 15 . The device of claim 14 , wherein, when the processor determines that the first data element associated with the debug indicator is in the data stream, the processor is further configured to identify a debug event associated with the first data element as one of a breakpoint and a probe point.
16. 16 . The device of claim 15 , wherein the processor is configured to halt execution of the program in response to identifying the debug event as a breakpoint.
17. 17 . The device of claim 15 , wherein the processor is configured to initiate and manage a trace stream in response to identifying the debug event as a probe point.
18. 18 . The device of claim 12 , wherein the streaming engine is further configured to: retrieve a next data element of the data elements using the address generated by the address generator for the next data element, and determine, for the next data element, whether the stored debug event criteria match a current state of the loop counters.
19. 19 . The device of claim 12 , wherein the streaming engine includes debug event detection circuitry coupled to the address generator.
20. 20 . The device of claim 19 , wherein the debug event detection circuitry includes detection logic coupled to the address generator, and event generation logic coupled to the detection logic.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of, and claims the benefit of priority under 35 U.S.C. § 120 on, U.S. application Ser. No. 18/354,166, filed Jul. 18, 2023 (now U.S. Pat. No. 12,105,616), which is a continuation of, and claims the benefit of priority under 35 U.S.C. § 120 on, U.S. application Ser. No. 17/352,444, filed Jun. 21, 2021 (now U.S. Pat. No. 11,755,456), which is a continuation of, and claims the benefit of priority under 35 U.S.C. § 120 on, U.S. application Ser. No. 16/181,894, filed Nov. 6, 2018 (now U.S. Pat. No. 11,042,468), all of which are incorporated by reference herein. TECHNICAL FIELD This relates to tracking debug events from an autonomous module through a data pipeline to a processor coupled to the autonomous module. BACKGROUND Digital signal processors (DSP) are optimized for processing streams of data that may be derived from various input signals, such as sensor data, a video stream, a voice channel, radar signals, biomedical signals, etc. Digital signal processors operating on real-time data typically receive an input data stream, perform a filter function on the data stream (such as encoding or decoding) and output a transformed data stream. The system is called real-time because the application fails if the transformed data stream is not available for output when scheduled. Typical video encoding requires a predictable but non-sequential input data pattern. A typical application requires memory access to load data registers in a data register file and then supply data from the data registers to functional units which preform the data processing. One or more DSP processing cores may be combined with various peripheral circuits, blocks of memory, etc. on a single integrated circuit (IC) die to form a system on chip (SoC). The advent of SOC architectures for embedded systems has created many challenges for the software development systems used to develop and debug software applications that execute on these architectures. These systems may include multiple interconnected processors that share the use of on-chip and off-chip memory. A processor may include some combination of instruction cache (ICache) and data cache (DCache) to improve processing. Furthermore, multiple processors, with memory being shared among them, may be incorporated in a single embedded system. The processors may physically share the same memory without accessing data or executing code located in the same memory locations or they may use some portion of the shared memory as common shared memory. Various techniques may be used to debug and trouble shoot software programs being executed on a SoC, such as software breakpoints, hardware breakpoints, software probe points, hardware probe points, etc. Software breakpoints are generally implemented with a special breakpoint instruction that replaces the actual instruction in memory and allow instruction processing to be halted when the breakpoint instruction is encountered. When a software breakpoint is set at a selected memory location during the debug process, the instruction at that memory location is saved in a breakpoint table and is replaced by the special breakpoint instruction. When the software breakpoint is cleared, the saved instruction is written back into the memory location. Software probe points are similar to breakpoints but instead of causing a processor to halt, some other debug action is taken such as managing a trace stream and/or advancing a counter. Hardware breakpoints and probe points may use hardware comparators to compare a designated instruction counter address, data address, etc. and to cause processing to halt for a breakpoint event or to manage a trace stream for a probe point event. SUMMARY Devices and methods are provided for identifying a debug event associated with a data element of a data stream, and performing debugging when a processor executes a software program in connection with the data stream. The debug event is tracked through a data pipeline to the processor. In an embodiment, the debug event is acted on only when the processor is ready to consume the data element associated with the debug event. In an embodiment, the debug event is determined by monitoring iteration counts of loop counters associated with an address generator and comparing the iteration counts to respective stored count values. In an example, a streaming engine includes an address generator that includes loop counters configured to generate respective iteration counts; and debug event detection circuitry coupled to the address generator. The debug event detection circuitry includes storage configured to store a respective count value and a respective bypass indicator for each of the loop counters; a set of comparators coupled to the storage and the loop counters; and event generation logic coupled to the storage and to the set of comparators, the event generation logic configured to generate a debug event based on cu