US-12625798-B2 - Apparatus and method for address generation, data buffer, and artificial intelligence chip

US12625798B2US 12625798 B2US12625798 B2US 12625798B2US-12625798-B2

Abstract

Disclosed are an apparatus and a method for address generation, a data buffer, and an artificial intelligence chip. The apparatus includes address generating circuits, including N first address generating circuits and M second address generating circuits, where an n-th first address generating circuit generates a first address y n of each element in each of first matrices required for computations on an n-th first dimension according to y n =floor(a n x n +b n )×T n , and the first matrices are distributed along M second dimensions; and an m-th second address generating circuit generates a second address y m of each first matrix on an m-th second dimension according to y m =floor(a m x m +b m )×T m ; and an address combining circuit generating an address for accessing each element in each first matrix by combining the second address of each first matrix on the M second dimensions and the first address of each element in each first matrix on N first dimensions.

Inventors

Li Jiao
Kuen Hung Tsoi
Xinyu NIU

Assignees

SHENZHEN CORERAIN TECHNOLOGIES CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230316
Priority Date: 20220318

Claims (13)

1 . An apparatus for address generation, used in a data buffer included in an artificial intelligence (AI) chip, the AI chip including a computation circuit, and the data buffer including a storage circuit, the apparatus comprising: a plurality of address generating circuits, comprising: N first address generating circuits corresponding to N first dimensions on a one-to-one basis, wherein an n-th first address generating circuit is configured to generate a first address y n of each element in each first matrix in a plurality of first matrices required for computations on an n-th first dimension according to a function y n =floor(a n x n +b n )×T n , where 1≤n≤N, elements at different positions on the n-th first dimension correspond to different values of x n , values of a n , b n and T n are such that the different values of x n correspond to different values of y n to ensure a unique address for each element on the n-th first dimension, and the plurality of first matrices are distributed along M second dimensions; and M second address generating circuits different from the N first address generating circuits and corresponding to the M second dimensions on a one-to-one basis, wherein an m-th second address generating circuit is configured to generate a second address y m of each first matrix on an m-th second dimension according to a function y m =floor(a m x m +b m )×T n , where 1≤m≤M, the first matrices at different positions on the m-th second dimension correspond to different values of x m , and values of a m , b m and T m are such that the different values of x m correspond to different values of y m to ensure a unique address for each element on the m-th second dimension; and an address combining circuit configured to generate an address for accessing each element in each first matrix from the storage circuit by combining the second address of each first matrix on the M second dimensions and the first address of each element in each first matrix on N first dimensions, the address being configured to instruct the storage circuit to sequentially output each element to the computation circuit according to the address, such that the computation circuit accesses the element and performs a corresponding computation.
2 . The apparatus for address generation according to claim 1 , wherein the n-th first address generating circuit comprises: a first output circuit configured to output a value of x n corresponding to each element in each first matrix; and a first arithmetic circuit configured to calculate a first intermediate address IA n of each element in each first matrix on the n-th first dimension on a basis of a formula IA n =floor(a n )×T n ×x n +floor(b n )×T n , and for any one element, calculate the first address y n on a basis of a formula y n =IA n +floor((a n −floor(a n ))×x n )×T n , where IA n ≠floor(a n x n +b n )×T n .
3 . The apparatus for address generation according to claim 2 , wherein the first arithmetic circuit comprises: a first address adder configured to calculate the first intermediate address IA n of each element on a basis of the formula IA n =floor(a n )×T n ×x n +floor(b n )×T n ; a first adder configured to calculate an offset value OV n of each element in each first matrix on the n-th first dimension on a basis of a formula OV n =floor((a n −floor(a n ))×x n ); a comparator configured to determine, for any one element, whether an absolute value of the offset value |OV n | is greater than or equal to 1, send a first indication signal in a case of |OV n |≥1, and send a second indication signal in a case of |OV n |<1; and a second address adder configured to calculate the first address y n of the any one element on a basis of the formula y n =IA n +floor((a n −floor(a n ))×x n )×T n in response to the first indication signal, and take the first intermediate address IA n of the any one element is as the first address y n in response to the second indication signal.
4 . The apparatus for address generation according to claim 2 , wherein x n corresponding to each element in each first matrix is an integer greater than or equal to 0, and a difference between the values of x n corresponding to any two adjacent elements on the n-th first dimension is consistent.
5 . The apparatus for address generation according to claim 4 , wherein the difference between the values of x n corresponding to any two adjacent elements on the n-th first dimension is 1.
6 . The apparatus for address generation according to claim 4 , wherein the first output circuit comprises a counter.
7 . The apparatus for address generation according to claim 1 , wherein the m-th second address generating circuit comprises: a second output circuit configured to output x m corresponding to each first matrix; a second arithmetic circuit configured to calculate a second intermediate address IA m of each first matrix on the m-th second dimension on a basis of a formula IA m =floor(a m )×T m ×x m +floor(b m )×T m , and for any one first matrix, calculate the second address y m on a basis of a formula y m =IA m +floor((a m −floor(a m ))×x m )×T m , where IA m ≠floor(a m x m +b m )×T m .
8 . The apparatus for address generation according to claim 1 , wherein each first matrix comprises elements at P positions distributed along the n-th first dimension, where P≥2, an element at an i-th position is adjacent to an element at an (i+1)-th position in the elements at the P positions, and 1≤i≤P−1; the plurality of first matrices comprise first matrices at Q positions distributed along the m-th second dimension, where Q≥2, a first matrix at a j-th position is adjacent a first matrix at a (j+1)-th position in the first matrices at the Q positions, and 1≤j≤Q−1; wherein the n-th first address generating circuit is configured to sequentially generate the first address y n of each element in each first matrix in an order from a 1st position to a P-th position, and the m-th second address generating circuit is configured to sequentially generate the second address y m of each first matrix in an order from a 1st position to a Q-th position.
9 . The apparatus for address generation according to claim 8 , wherein a (k−1)-th second address generating circuit is configured to generate the second address of the first matrix at each position on a (k−1) second dimension when a k-th second address generating circuit generates the second address of the first matrix at any position on a k-th second dimension, where 2≤k≤M; an N-th first address generating circuit is configured to generate the first address of the element at each position on the N-th first dimension when a 1st second address generating circuit generates the second address of the first matrix at any position on a 1st second dimension; and an (s−1)-th first address generating circuit is configured to generate the first address of the element at each position on an (s−1)-th first dimension when an s-th first address generating circuit generates the first address of the element at any position on an s-th first dimension, where 2≤s≤N.
10 . The apparatus for address generation according to claim 1 , wherein the elements at same positions on the n-th first dimension in each first matrix belong to the elements at same positions on the n-th first dimension in a second matrix; the second matrix comprises a third matrix, and at least some of the elements in each first matrix belong to the third matrix, wherein the elements in the third matrix are distributed along R third dimensions, and the R third dimensions comprise the N first dimensions and the M second dimensions; the plurality of address generating circuits comprise: R third address generating circuits corresponding to the R third dimensions on a one-to-one basis, wherein an r-th third address generating circuit is configured to generate a third address y r of each element on an r-th third dimension in the third matrix according to a function y r =floor(a r x r +b r )×T r , where 1≤r≤R, the elements at different positions on the r-th third dimension correspond to different values of x r , and values of a r , b r and T r are such that the different values of x r correspond to different values of y r ; wherein the address combining circuit is further configured to generate addresses for storing each element in the third matrix by combining the third addresses of each element in the third matrix on the R third dimensions, where the addresses for storing different elements in the third matrix are different.
11 . The apparatus for address generation according to claim 10 , wherein the N first dimensions and the M second dimensions comprise a same at least one dimension; the address combining circuit comprises: at least one second adder corresponding to the at least one dimension on a one-to-one basis, wherein each second adder is configured to add the first address of each element in each first matrix on a corresponding dimension to the second address of the first matrix on the corresponding dimension to obtain a fourth address of each element on the corresponding dimension; and an address combining sub-circuit is configured to: as to any one of the at least one dimension, determine whether the fourth address of each element on the any one dimension belongs to a set of addresses for the any one dimension, so as to obtain a determination result for the any one dimension, wherein the set of addresses for the any one dimension is composed of the third address of each element in the third matrix on the any one dimension; and as to any one element, in a case of a negative determination result for a certain dimension in the at least one dimension, adjust the fourth address on the certain dimension to be the third address in the set of addresses for the certain dimension; after the adjustment, add up the fourth address on the at least one dimension, the first address on the first dimensions other than the at least one dimension in the N first dimensions, and the second address on the second dimensions other than the at least one dimension in the M second dimensions, so as to obtain the address for accessing the any one element.
12 . The apparatus for address generation according to claim 1 , combined with a storage circuit to form a data buffer, the storage circuit configured to send each element in the plurality of first matrices according to the address for accessing each element in each first matrix, and store each element in the matrix according to the address for storing each element in the matrix.
13 . A method for address generation, used in a data buffer included in an artificial intelligence (AI) chip, the AI chip including a computation circuit, and the data buffer including a storage circuit, the method comprising: generating a first address y n of each element in each first matrix in the plurality of first matrices required for computations on an n-th first dimension according to a function y n =floor(a n x n +b n )×T n by an n-th first address generating circuit in N first address generating circuits, the N first address generating circuits corresponding to N first dimensions on a one-to-one basis, where 1≤n≤N, elements at different positions on the n-th first dimension correspond to different values of x n , values of a n , b n and T n are such that the different values of x n correspond to different values of y n to ensure a unique address for each element on the n-th first dimension, and the plurality of first matrices are distributed along M second dimensions; generating a second address y m of each first matrix on an m-th second dimension according to a function y m =floor(a m x m +b m )×T m by an m-th second address generating circuit in M second address generating circuits, the M second address generating circuits being different from the N first address generating circuits and corresponding to M second dimensions on a one-to-one basis, where 1≤m≤M, the first matrices at different positions on the m-th second dimension correspond to different values of x m , and values of a m , b m and T m are such that the different values of x m correspond to different values of y m to ensure a unique address for each element on the m-th second dimension; and generating an address for accessing each element in each first matrix from the storage circuit by an address combining circuit that combines the second address of each first matrix on the M second dimensions and the first address of each element in each first matrix on N first dimensions, the address being configured to instruct the storage circuit to sequentially output each element to the computation circuit according to the address, such that the computation circuit accesses the element and performs a corresponding computation.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application claims the benefit of Chinese Patent Application No. 202210268845.3 filed on Mar. 18, 2022, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD The present disclosure relates to the field of artificial intelligence and, more particularly, to an apparatus and a method for address generation, a data buffer, and an artificial intelligence chip. BACKGROUND In recent years, artificial intelligence (AI) has been widely used in various industries. However, AI applications involve various complex computations. In the related art, AI chips may perform these computations to improve computational efficiency. The AI chip includes a data buffer for buffering data and a computation circuit for performing computations. In the process of performing computations, the computation circuit can directly access data required for computations from the data buffer, so that the computational efficiency can be improved. SUMMARY The inventors have noted that in the related art, the versatility of AI chips is not high enough, that is, AI chips can only be used to perform one or a few types of computations and cannot be universally applied to a variety of computations. The inventors have figured out that a major reason is the low versatility of an apparatus for address generation in the data buffer. Specifically, the apparatus for address generation generates the addresses of the elements in the matrix in a manner tailored to the matrix required for computation, so that the computation circuit accesses the corresponding elements and performs computation. However, due to differences in the matrices required for different computations (e.g., dimensions of a matrix, the number of elements at different positions on each dimension of a matrix, etc.), the apparatus for address generation customized for one type of matrices required for some of the computations is unable to generate addresses of elements in another type of matrices required for the others of the computations, and thus the AI chip is unable to perform the other computations. In the related art, a plurality of apparatuses for address generation tailored to different matrices required for computations may be provided so that the AI chip can perform a variety of computations. However, in view of design complexity and area limitations, only a limited number of apparatuses for address generation can be provided, and the versatility is still not up to expectations. To solve the above problems, embodiments of the present disclosure provide the following technical solution. According to an aspect of the embodiments of the present disclosure, an apparatus for address generation is provided, including: a plurality of address generating circuits and an address combining circuit, wherein the plurality of address generating circuits include N first address generating circuits and M second address generating circuits. The N first address generating circuits correspond to N first dimensions on a one-to-one basis, wherein an n-th first address generating circuit is configured to generate a first address yn of each element in each first matrix in a plurality of first matrices required for computations on an n-th first dimension according to a function yn=floor(anxn+bn)×Tn, where 1≤n≤N, elements at different positions on the n-th first dimension correspond to different values of xn, values of an, bn and Tn are such that the different values of xn correspond to different values of yn, and the plurality of first matrices are distributed along M second dimensions. The M second address generating circuits are different from the N first address generating circuits and correspond to the M second dimensions on a one-to-one basis, wherein an m-th second address generating circuit is configured to generate a second address ym of each first matrix on an m-th second dimension according to a function ym=floor(amxm+bm)×Tm, where 1≤m≤M, the first matrices at different positions on the m-th second dimension correspond to different values of xm, and values of am, bm and Tm are such that the different values of xm correspond to different values of ym. The address combining circuit is configured to generate an address for accessing each element in each first matrix by combining the second address of each first matrix on the M second dimensions and the first address of each element in each first matrix on the N first dimensions. According to another aspect of the embodiments of the present disclosure, a method for address generation is provided, including: generating a first address yn of each element in each first matrix in the plurality of first matrices required for computations on an n-th first dimension according to a function yn=floor(anxn+bn)×Tn by an n-th first address generating circuit in N first address generating circuits, the N first address generating circuits corresponding to N first dimensions