US-12625799-B2 - Memory device with staggered access

Abstract

A memory device supports low power operation by facilitating staggered access to row segments within a row of a memory bank. Upon receiving an activate command to activate a row, the memory device sequentially activates a plurality of local wordlines associated with the row with a stagger interval between activations. Upon receiving an access command associated with the activated row, the memory device sequentially initiates column operations for respective row segments with the same stagger interval between the column operations. The memory device may furthermore facilitate error correction code operations in a staggered manner by sequentially performing computations associated with the different row segments.

Inventors

• Torsten Partsch

Assignees

• RAMBUS INC.

Dates

Publication Date

20260512

Application Date

20241018

Claims (20)

1. 1 . A memory device comprising: an array of memory cells; a master wordline for a row of the array; a plurality of local wordlines independently drivable from the master wordline, each of the local wordlines associated with respective row segments of the row; command logic to sequentially activate respective ones of the plurality of local wordlines responsive to an activate command for the row with a stagger interval between activations of the plurality of local wordlines, and the command logic further to receive a first access command and to sequentially initiate column operations to access data from the respective row segments with the stagger interval between the column operations.
2. 2 . The memory device of claim 1 , wherein the command logic is configured to execute a second access command having a same burst order as the first access command, and wherein the command logic enforces a first minimum time interval between the first access command the second access command; and wherein the command logic is configured to execute a third access command having a different burst order than the second access command, and wherein the command logic enforces a second minimum time interval between the second access command the third access command, the second minimum time interval longer than the first minimum time interval.
3. 3 . The memory device of claim 1 , wherein the stagger interval is at least as long as a burst period associated with the first access command.
4. 4 . The memory device of claim 1 , wherein the command logic is configurable between a staggered access mode and a non-staggered access mode, wherein in the non-staggered access mode, the command logic is configured to concurrently activate the respective ones of the plurality of local wordlines responsive to the activation of the master wordline, and wherein the command logic is configured to concurrently initiate the column operations.
5. 5 . The memory device of claim 4 , wherein a minimum latency between initiating the column operations and outputting the data is the same in the staggered access mode and the non-staggered access mode.
6. 6 . The memory device of claim 4 , wherein a minimum interval between the activation of the master wordline and a subsequent precharge operation is longer in the staggered access mode than the non-staggered access mode.
7. 7 . The memory device of claim 1 , wherein the command logic includes a register for controlling a duration of the stagger interval.
8. 8 . The memory device of claim 1 , further comprising: error correction code logic to obtain the data from the respective row segments in a staggered sequence of data segments, and to sequentially perform an error correction code function on each of the data segments to generate an error correction code for the data.
9. 9 . A memory module comprising: a plurality of memory devices on a printed circuit board, wherein the plurality of memory devices each comprise: an array of memory cells; a master wordline for a row of the array; a plurality of local wordlines independently drivable from the master wordline, each of the local wordlines associated with respective row segments of the row; and command logic to sequentially activate respective ones of the plurality of local wordlines responsive to activate command for the row with a stagger interval between activations of the plurality of local wordlines, and the command logic further to receive a first access command and to sequentially initiate column operations to access data from the respective row segments with the stagger interval between the column operations.
10. 10 . The memory module of claim 9 , wherein the command logic is configured to execute a second access command having a same burst order as the first access command, and wherein the command logic enforces a first minimum time interval between the first access command the second access command; and wherein the command logic is configured to execute third second access command having a different burst order than the second access command, and wherein the command logic enforces a second minimum time interval between the second access command and the third access command, the second minimum time interval longer than the first minimum time interval.
11. 11 . The memory module of claim 9 , wherein the stagger interval is at least as long as a burst period associated with the first access command.
12. 12 . The memory module of claim 9 , wherein the command logic is configurable between a staggered access mode and a non-staggered access mode, wherein in the non-staggered access mode, the command logic is configured to concurrently activate the respective ones of the plurality of local wordlines responsive to the activation of the master wordline, and wherein the command logic is configured to concurrently initiate the column operations.
13. 13 . The memory module of claim 12 , wherein a minimum latency between initiating the column operations and outputting the data is the same in the staggered access mode and the non-staggered access mode.
14. 14 . The memory module of claim 12 , wherein a minimum interval between the activation of the master wordline and a subsequent precharge operation is longer in the staggered access mode than the non-staggered access mode.
15. 15 . The memory module of claim 9 , wherein the command logic includes a register for controlling a duration of the stagger interval.
16. 16 . The memory module of claim 9 , wherein the plurality of memory devices further each comprise: error correction code logic to obtain the data from the respective row segments in a staggered sequence of data segments, and to sequentially perform an error correction code function on each of the data segments to generate an error correction code for the data.
17. 17 . A method for operating a memory device comprising: receiving a first activate command via a command interface of the memory device for activating a master wordline for a row of an array of memory cells; responsive to the first activate command, sequentially activating a plurality of local wordlines with a stagger interval between activations of the plurality of local wordlines, wherein the plurality of local wordlines are independently drivable from the master wordline; receiving a first access command from the command interface; and responsive to the first access command, sequentially initiating first column operations to access data from respective row segments associated with the plurality of local wordlines with the stagger interval between the column operations.
18. 18 . The method of claim 17 , further comprising: receiving a second access command from the command interface having a same burst order as the first access command; executing the second access command while enforcing a first minimum time interval between executions of the first access command the second access command; receiving a third access command from the command interface having a different burst order than the second access command; and executing the third access command while enforcing a second minimum time interval between executions of the second access command the third access command, wherein the second minimum time interval longer than the first minimum time interval.
19. 19 . The method of claim 17 , wherein the stagger interval is at least as long as a burst period associated with the first access command.
20. 20 . The method of claim 17 , further comprising: switching operation of the memory device from a staggered access mode to a non-staggered access mode; receiving a second activate command via the command interface in the non-staggered access mode; executing the second activate command by concurrently activating the plurality of local wordlines; receiving a second access command via the command interface in the non-staggered access mode; and executing the second access command by concurrently initiating second column operations associated with each of the row segments.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63/596,685 filed on Nov. 7, 2023, which is incorporated by reference herein in its entirety. BACKGROUND Memory devices such as Dynamic Random-Access Memory (DRAM) are used in a wide variety of electronic devices. In battery powered systems or other low power applications, it can be desirable to reduce peak current of the memory device to lower power consumption, reduce stress on electronic components, and reduce undesirable electromagnetic effects. BRIEF DESCRIPTION OF THE DRAWINGS The teachings of the embodiments herein can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. FIG. 1 is an example architecture of a bank for a memory device that supports staggered access to row segments of a row. FIG. 2 is an example architecture of a memory device that supports staggered access to row segments of a row. FIG. 3 is an example embodiment of a bank layout of a memory device in an x4 configuration that supports staggered access to row segments of a row. FIG. 4 is an example embodiment of a bank layout of a memory device in an x8 configuration that supports staggered access to row segments of a row. FIG. 5 is a timing diagram associated with staggered access to row segments in a memory device. FIG. 6 is a timing diagram associated with back-to-back accesses to a row of a memory device with staggered access, when the burst order is kept the same. FIG. 7 is a timing diagram associated with back-to-back accesses to a row of a memory device with staggered access, when the burst order changes. FIG. 8 is a block diagram of error correction code logic for a memory device that enables staggered access. FIG. 9 is a flowchart illustrating an example embodiment of a process for operating a memory device in a staggered access mode. FIG. 10 is an example embodiment of a memory module supporting staggered access. DETAILED DESCRIPTION A memory device supports low power operation by facilitating staggered access to row segments within a row of a memory bank. Upon receiving an activate command to activate a row, the memory device sequentially activates a plurality of local wordlines associated with the row with a stagger interval between activations. Upon receiving an access command associated with the activated row, the memory device sequentially initiates column operations for respective row segments with the same stagger interval between the column operations. The memory device may furthermore facilitate error correction code operations in a staggered manner by sequentially performing computations associated with the different row segments. FIG. 1 illustrates an example schematic of a bank 100 for a memory device, such as a dynamic random-access memory (DRAM). The bank 100 includes an array of cells organized into rows and columns. The bank 100 may furthermore be organized into a plurality of segments 150 (e.g., four segments 150-1, 150-2, 150-3, 150-4) that each include a subset of the columns. FIG. 1 expressly illustrates only a single column in each segment 150, but segments 150 may include any number of columns with similar structures. Similarly, FIG. 1 expressly illustrates only a single row of the bank 100, but the bank 100 may include any number of rows with similarly structures. Each row is associated with a master wordline (MWL) 102 that provides a master activation signal and each segment 150 of a row is associated with a respective local wordline (LWL) 104 driven by a respective local wordline driver 106. The local wordline drivers 106 are controlled by respective local wordline select (LWLS) lines 108 that selectively couple the master wordline 102 to the respective local wordlines 104. The local wordline select lines 108 may be shared between multiple rows and operate in conjunction with the master wordline 102 per row to activate a selected local wordline 104. Thus, a given local wordline 104 is activated when the corresponding master wordline 102 is activated and when the corresponding local wordline select line 108 is activated. This architecture enables local wordlines 104 in the same row to be activated or deactivated independently. The columns of the bank 100 are associated with respective bitlines (BL) (or bitline pairs) 112 that each couple the cells in an activated local wordline 104 to a set of respective local sense amplifiers (LSAs) 110. The bitlines 112 and local sense amplifiers 110 may be shared across cells within the same column because only one row is activated at a time. The local sense amplifiers 110 sense voltages of the corresponding bitlines 112 during read operations and transfer voltages to the bitlines 112 for writing to cells during write operations. The local sense amplifiers 110 are coupled to respective local input/output (LIO) lines 114 associated with each local wordline 104, which couple to respectiv