US-12625800-B1 - Data storage device and method for direct data quantization in multi-level-cell memory

Abstract

In a data storage device with a multi-level-cell memory, bits of data are stored in different levels of each of the memory cells. In some situations, a quantized version of the stored data (e.g., the most-significant bits) may be requested. Responding to such a request can involve reading all levels of the memory cells to retrieve a full version of the data and then selectively providing only the quantized version. To improve performance, the data is stored in the memory in an interleaved manner in which the quantized version of the data is stored in the same level(s) instead of being spread across all levels of the memory cells. That way, when the quantized version of the data is later requested, only the relevant level(s) are sensed, thereby avoiding the time and resources needed to read memory level(s) that do not store the quantized data.

Inventors

• Snehal Vithal Uphale
• Ramanathan Muthiah

Assignees

• SanDisk Technologies, Inc.

Dates

Publication Date

20260512

Application Date

20241113

Claims (19)

1. 1 . A data storage device comprising: a memory comprising multi-level memory cells; and one or more processors, individually or in combination, configured to: receive a request to store data; store the data in the multi-level memory cells, wherein each bit of a set of most-significant bits of the data is stored in a same memory cell level in each respective multi-level memory cell; in response to receiving a request to read a quantized version of the data, read the set of most-significant bits of the data stored in the same memory cell level of each respective multi-level memory cells without reading other bits of the data stored in at least one other memory cell level of the multi-level memory cells; and in response to receiving a request to read a non-quantized version of the data, read the other bits of the data stored in the at least one other memory cell level of the multi-level memory cells; wherein the other bits of the data stored in the at least one other memory cell level of the multi-level memory cells are read when the non-quantized version of the data is read but not when the quantized version of the data is read.
2. 2 . The data storage device of claim 1 , wherein: the set of most-significant bits of the data is stored in a first memory cell level of each respective multi-level memory cell; each bit of a set of next-most-significant bits of the data is stored at a second memory cell level in each respective multi-level memory cell; and the one or more processors, individually or in combination, are further configured to read both the set of most-significant bits of the data and the set of next-most-significant bits of the data in response to receiving the request to read the quantized version of the data.
3. 3 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to: in response to receiving the request to read the non-quantized version of the data: read the set of most-significant bits of the data from the same memory cell level in each respective multi-level memory cells; and read other bits of the data from other memory cell levels of the multi-level memory cells.
4. 4 . The data storage device of claim 1 , wherein: the multi-level memory cells comprise quad-level cells; and the set of most-significant bits of the data is stored in a page of the quad-level cells that requires a fewest number of memory senses.
5. 5 . The data storage device of claim 4 , wherein: a set of next-most-significant bits of the data is stored in an upper page of the quad-level cells.
6. 6 . The data storage device of claim 1 , wherein: the multi-level memory cells comprise quad-level cells; and the set of most-significant bits of the data is stored in an upper page of the quad-level cells.
7. 7 . The data storage device of claim 1 , wherein each bit of the set of most-significant bits of the data is stored in the same memory cell level in each respective multi-level memory cell in response to the request specifying a logical block address that is in a designated logical block address range.
8. 8 . The data storage device of claim 1 , wherein each bit of the set of most-significant bits of the data is stored in the same memory cell level in each respective multi-level memory cell in response to the request being received from a designated host.
9. 9 . The data storage device of claim 1 , wherein the data storage device is an artificial intelligence/machine learning (AI/ML) specialized data storage device.
10. 10 . The data storage device of claim 1 , wherein the data storage device is part of a security system.
11. 11 . The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.
12. 12 . In a data storage device comprising multi-level memory cells, a method comprising: receiving a request to store data; storing the data in the multi-level memory cells, wherein each bit of a set of most-significant bits of the data is stored in a same memory cell level in each respective multi-level memory cell; in response to receiving a request to read a quantized version of the data, reading the set of most-significant bits of the data stored in the same memory cell level of each respective multi-level memory cells without reading other bits of the data stored in at least one other memory cell level of the multi-level memory cells; and in response to receiving a request to read a non-quantized version of the data, reading the other bits of the data stored in the at least one other memory cell level of the multi-level memory cells; wherein the other bits of the data stored in the at least one other memory cell level of the multi-level memory cells are read when the non-quantized version of the data is read but not when the quantized version of the data is read.
13. 13 . The method of claim 12 , further comprising: in response to receiving the request to read the non-quantized version of the data: sensing all memory cell levels in the multi-level memory cells; and responding to the request to read the non-quantized version of the data by returning bits sensed from all of the memory cell levels in the multi-level memory cells.
14. 14 . The method of claim 12 , wherein: the multi-level memory cells comprise quad-level cells; and the set of most-significant bits of the data is stored in a page of the quad-level cells that requires a fewest number of memory senses.
15. 15 . The method of claim 14 , wherein: a set of next-most-significant bits of the data is stored in an upper page of the quad-level cells.
16. 16 . The method of claim 12 , wherein: the multi-level memory cells comprise quad-level cells; and the set of most-significant bits of the data is stored in an upper page of the quad-level cells.
17. 17 . The method of claim 12 , wherein each bit of the set of most-significant bits of the data is stored in the same memory cell level in each respective multi-level memory cell in response to a write request for the data specifying a logical block address that is in a designated logical block address range.
18. 18 . The method of claim 12 , wherein each bit of the set of most-significant bits of the data is stored in the same memory cell level in each respective multi-level memory cell in response to a write request for the data being received from a designated host.
19. 19 . A data storage device comprising: a memory comprising multi-level memory cells; and means for: receiving a request to store data; storing the data in the multi-level memory cells, wherein each bit of a set of most-significant bits of the data is stored in a same memory cell level in each respective multi-level memory cell; in response to receiving a request to read a quantized version of the data, reading the set of most-significant bits of the data stored in the same memory cell level of each respective multi-level memory cells without reading other bits of the data stored in at least one other memory cell level of the multi-level memory cells; and in response to receiving a request to read a non-quantized version of the data, reading the other bits of the data stored in the at least one other memory cell level of the multi-level memory cells; wherein the other bits of the data stored in the at least one other memory cell level of the multi-level memory cells are read when the non-quantized version of the data is read but not when the quantized version of the data is read.

Description

BACKGROUND Computational resource requirements of artificial intelligence (AI) systems are typically high. A device that processes data and derives inferences using an AI engine should have sufficient computational, network, and storage bandwidth. Good storage throughput is desired to continuously feed data to an AI model so that it can perform optimally. In resource-constrained devices (such as security cameras, smart phones and edge devices), a lack of storage bandwidth can severely impact AI performance. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a block diagram of a data storage device of an embodiment. FIG. 1B is a block diagram illustrating a storage module of an embodiment. FIG. 1C is a block diagram illustrating a hierarchical storage system of an embodiment. FIG. 2A is a block diagram illustrating components of the controller of the data storage device illustrated in FIG. 1A according to an embodiment. FIG. 2B is a block diagram illustrating components of the data storage device illustrated in FIG. 1A according to an embodiment. FIG. 3 is a block diagram of a host and a data storage device of an embodiment. FIG. 4 is an illustration of a security system of an embodiment. FIG. 5 is a table illustrating an example coding scheme of an embodiment. FIG. 6 is an example of data storage in quad-level cell (QLC) pages of an embodiment. FIG. 7 is a table illustrating an example storage method of an embodiment. FIG. 8 is a table illustrating an example storage method of an embodiment. FIG. 9 is a table illustrating an example storage method of an embodiment. FIG. 10 is a table illustrating an example storage method of an embodiment. FIG. 11 is a table illustrating a number of sensing steps needed to read 16-bit quantized data in an embodiment. FIG. 12 is an illustration of a host and a data storage device of an embodiment. FIG. 13 is an illustration of a communication method of an embodiment. FIG. 14 is a flow sequence diagram of an embodiment. FIG. 15 is an illustration of hosts and a data storage device of an embodiment. FIG. 16 is a flow sequence diagram of an embodiment. DETAILED DESCRIPTION The following embodiments generally relate to a data storage device and method for direct data quantization in multi-level cell memory. In one embodiment, a data storage device is provided comprising a memory comprising multi-level memory cells and one or more processors. The one or more processors, individually or in combination, are configured to: receive a request to store data; and store the data in the multi-level memory cells, wherein each bit of a set of most-significant bits of the data is stored in a same memory cell level in each respective multi-level memory cell. In another embodiment, a method is provided that is performed in a data storage device comprising multi-level memory cells. The method comprises: interleaving data in the multi-level memory cells such that each bit of a set of most-significant bits of the data is stored in a first memory cell level in each respective multi-level memory cell; receiving a request for a quantized version of the data; and in response to receiving the request for the quantized version of the data: sensing the first memory cell level in each respective multi-level memory cell without sensing at least one other memory cell level in each respective multi-level memory cell; and responding to the request by returning bits sensed from the first memory cell level in each respective multi-level memory cell. In yet another embodiment, a data storage device is provided comprising: a memory comprising multi-level memory cells; and means for reducing sense time to read a quantized version of data stored in the memory by storing each bit of a set of most-significant bits of the data in a same memory cell level in each respective multi-level memory cell. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings. EMBODIMENTS The following embodiments relate to a data storage device (DSD). As used herein, a “data storage device” refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, hybrid drives, etc. Details of example DSDs are provided below. Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in FIGS. 1A-1C. It should be noted that these are merely examples and that other implementations can be used. FIG. 1A is a block diagram illustrating the data storage device 100 according to an embodiment. Referring to FIG. 1A, the data storage device 100 in this example includes a controller 102 coupled with a non-volatile memory that may be made up of one or more non-volatile memory die 104. As used herein, the term die refers to the collection of non-volatile memory cells, and associate