US-12625801-B2 - Data processing method, apparatus, and system, computing device, and storage medium

Abstract

The present disclosure relates to data processing methods, computer devices, and non-transitory computer-readable storage media. In an example method, at least one processor obtains an instruction sequence of an application program, identifies an execution sequence of read/write instructions in the instruction sequence based on the instruction sequence, and executes the read/write instructions based on the identified execution sequence.

Inventors

• Rutao ZHANG
• Di Yu
• Kai Hou

Assignees

• HUAWEI TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260512

Application Date

20240607

Priority Date

20211210

Claims (20)

1. 1 . A method for data processing, wherein the method is performed by at least one processor of a computing device, and the method comprises: obtaining an instruction sequence of an application program, wherein the instruction sequence comprises a plurality of instructions, the plurality of instructions comprise read/write instructions for performing at least one of a read operation or a write operation on one or more memories of the computing device, and the application program is deployed in the computing device; identifying an execution sequence of the read/write instructions based on the instruction sequence; and executing the read/write instructions based on the execution sequence, wherein: the read/write instructions comprise at least one of a read instruction for performing the read operation on the one or more memories or a write instruction for performing the write operation on the one or more memories, the read instruction has a first semantic, and the write instruction has a second semantic, the first semantic indicates that a first instruction in the instruction sequence is executed after the read instruction is executed, wherein the first semantic prevents any instruction that is arranged after the read instruction in the instruction sequence from being executed before the read instruction is executed; and the second semantic indicates that a second instruction in the instruction sequence is executed before execution of the write instruction is completed, wherein the second semantic prevents any instruction that is arranged before the write instruction in the instruction sequence from being executed after the write instruction is executed, the read instruction is fetched through compiling an extended memory read instruction, the extended memory read instruction has the first semantic, and the extended memory read instruction is an instruction that is added to an instruction set of the at least one processor and that is used to instruct to read memory data; and the write instruction is fetched through compiling an extended memory write instruction, the extended memory write instruction has the second semantic, and the extended memory write instruction is an instruction that is added to the instruction set and that is used to instruct to write the memory data.
2. 2 . The method according to claim 1 , wherein the identifying an execution sequence of the read/write instructions based on the instruction sequence comprises: identifying an arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions.
3. 3 . The method according to claim 2 , wherein the identifying an arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions comprises: identifying, in a sequential memory access mode, the arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions, wherein the sequential memory access mode requires that the execution sequence of the read/write instructions be consistent with the arrangement sequence of the read/write instructions in the instruction sequence.
4. 4 . The method according to claim 1 , wherein: for the first semantic, the first instruction is arranged after the read instruction in the instruction sequence; and for the second semantic, the second instruction is arranged before the write instruction in the instruction sequence.
5. 5 . The method according to claim 1 , wherein: the extended memory read instruction comprises at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, or a fourth extended memory read instruction, and the extended memory write instruction comprises at least one of a first extended memory write instruction or a second extended memory write instruction; none of addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction comprises an unscaled immediate addressing mode, and all of the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction support the unscaled immediate addressing mode; the first extended memory read instruction is used to instruct to determine a storage address in the one or more memories based on at least one of the supported addressing modes, and read a first byte quantity of data in the determined storage address to a first destination register; the second extended memory read instruction is used to instruct to determine a storage address in the one or more memories based on at least one of the supported addressing modes, read a second byte quantity of data in the determined storage address to a second destination register, and fill a remaining bit of the second destination register with a sign bit of the read data; the third extended memory read instruction is used to instruct to determine a storage address in the one or more memories based on the unscaled immediate addressing mode, and read a first byte quantity of data in the determined storage address to a third destination register; the fourth extended memory read instruction is used to instruct to determine a storage address in the one or more memories based on the unscaled immediate addressing mode, read a second byte quantity of data in the determined storage address to a fourth destination register, and fill a remaining bit of the fourth destination register with a sign bit of the read data; the first extended memory write instruction is used to instruct to determine a storage address in the one or more memories based on at least one of the supported addressing modes, and write a third byte quantity of data in a first source register to the determined storage address; and the second extended memory write instruction is used to instruct to determine a storage address in the one or more memories based on the unscaled immediate addressing mode, and write a third byte quantity of data in a second source register to the determined storage address.
6. 6 . The method according to claim 5 , wherein: the first byte quantity comprises one byte, two bytes, four bytes, or eight bytes, the second byte quantity comprises one byte, two bytes, or four bytes, and the third byte quantity comprises one byte, two bytes, four bytes, or eight bytes; the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction comprise at least one of a scaled immediate addressing mode, a label addressing mode, or a register addressing mode, and an immediate used when address offset is performed in the scaled immediate addressing mode is a scaled operand in a corresponding instruction; and an immediate used when the address offset is performed in the unscaled immediate addressing mode is an operand in a corresponding instruction, and a value range of the operand is −256 to 256.
7. 7 . The method according to claim 1 , wherein: the read/write instructions comprise a second read instruction that is fetched through compiling a second extended memory read instruction, and the second extended memory read instruction is an instruction fetched through adding the first semantic to a general memory read instruction in an instruction set of the at least one processor; and the read/write instructions comprise a second write instruction that is fetched through compiling a second extended memory write instruction, and the second extended memory write instruction is an instruction fetched through adding the second semantic to a general memory write instruction in the instruction set.
8. 8 . The method according to claim 1 , wherein the read/write instructions comprise a third read instruction that is fetched through compiling a general memory read instruction in an instruction set of the at least one processor, and the read/write instructions comprise a third write instruction that is fetched through compiling a general memory write instruction in the instruction set of the at least one processor.
9. 9 . A computer device, comprising: at least one processor; and one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to perform operations comprising: obtaining an instruction sequence of an application program, wherein the instruction sequence comprises a plurality of instructions, the plurality of instructions comprise read/write instructions for performing at least one of a read operation or a write operation on the one or more memories of the computing device, and the application program is deployed in the computing device; identifying an execution sequence of the read/write instructions based on the instruction sequence; and executing the read/write instructions based on the execution sequence, wherein: the read/write instructions comprise at least one of a read instruction for performing the read operation on the one or more memories or a write instruction for performing the write operation on the one or more memories, the read instruction has a first semantic, and the write instruction has a second semantic, the first semantic indicates that a first instruction in the instruction sequence is executed after the read instruction is executed, wherein the first semantic prevents any instruction that is arranged after the read instruction in the instruction sequence from being executed before the read instruction is executed; and the second semantic indicates that a second instruction in the instruction sequence is executed before execution of the write instruction is completed, wherein the second semantic prevents any instruction that is arranged before the write instruction in the instruction sequence from being executed after the write instruction is executed, the read instruction is fetched through compiling an extended memory read instruction, the extended memory read instruction has the first semantic, and the extended memory read instruction is an instruction that is added to an instruction set of the at least one processor and that is used to instruct to read memory data; and the write instruction is fetched through compiling an extended memory write instruction, the extended memory write instruction has the second semantic, and the extended memory write instruction is an instruction that is added to the instruction set and that is used to instruct to write the memory data.
10. 10 . The computer device according to claim 9 , wherein the identifying an execution sequence of the read/write instructions based on the instruction sequence comprises: identifying an arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions.
11. 11 . The computer device according to claim 10 , wherein the identifying an arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions comprises: identifying, in a sequential memory access mode, the arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions, wherein the sequential memory access mode requires that the execution sequence of the read/write instructions be consistent with the arrangement sequence of the read/write instructions in the instruction sequence.
12. 12 . The computer device according to claim 9 , wherein: for the first semantic, the first instruction is arranged after the read instruction in the instruction sequence; and for the second semantic, the second instruction is arranged before the write instruction in the instruction sequence.
13. 13 . The computer device according to claim 9 , wherein: the extended memory read instruction comprises at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, or a fourth extended memory read instruction, and the extended memory write instruction comprises at least one of a first extended memory write instruction or a second extended memory write instruction; none of addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction comprises an unscaled immediate addressing mode, and all of the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction support the unscaled immediate addressing mode; the first extended memory read instruction is used to instruct to determine a storage address in the one or more memories based on at least one of the supported addressing modes, and read a first byte quantity of data in the determined storage address to a first destination register; the second extended memory read instruction is used to instruct to determine a storage address in the one or more memories based on at least one of the supported addressing modes, read a second byte quantity of data in the determined storage address to a second destination register, and fill a remaining bit of the second destination register with a sign bit of the read data; the third extended memory read instruction is used to instruct to determine a storage address in the one or more memories based on the unscaled immediate addressing mode, and read a first byte quantity of data in the determined storage address to a third destination register; the fourth extended memory read instruction is used to instruct to determine a storage address in the one or more memories based on the unscaled immediate addressing mode, read a second byte quantity of data in the determined storage address to a fourth destination register, and fill a remaining bit of the fourth destination register with a sign bit of the read data; the first extended memory write instruction is used to instruct to determine a storage address in the one or more memories based on at least one of the supported addressing modes, and write a third byte quantity of data in a first source register to the determined storage address; and the second extended memory write instruction is used to instruct to determine a storage address in the one or more memories based on the unscaled immediate addressing mode, and write a third byte quantity of data in a second source register to the determined storage address.
14. 14 . The computer device according to claim 13 , wherein: the first byte quantity comprises one byte, two bytes, four bytes, or eight bytes, the second byte quantity comprises one byte, two bytes, or four bytes, and the third byte quantity comprises one byte, two bytes, four bytes, or eight bytes; the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction comprise at least one of a scaled immediate addressing mode, a label addressing mode, or a register addressing mode, and an immediate used when address offset is performed in the scaled immediate addressing mode is a scaled operand in a corresponding instruction; and an immediate used when the address offset is performed in the unscaled immediate addressing mode is an operand in a corresponding instruction, and a value range of the operand is −256 to 256.
15. 15 . The computer device according to claim 9 , wherein: the read/write instructions comprise a second read instruction that is fetched through compiling a second extended memory read instruction, and the second extended memory read instruction is an instruction fetched through adding the first semantic to a general memory read instruction in an instruction set of the at least one processor; and the read/write instructions comprise a second write instruction that is fetched through compiling a second extended memory write instruction, and the second extended memory write instruction is an instruction fetched through adding the second semantic to a general memory write instruction in the instruction set.
16. 16 . The computer device according to claim 9 , wherein the read/write instructions comprise a third read instruction that is fetched through compiling a general memory read instruction in an instruction set of the at least one processor, and the read/write instructions comprise a third write instruction that is fetched through compiling a general memory write instruction in the instruction set of the at least one processor.
17. 17 . A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores at least one piece of program code, and the at least one piece of program code is read by at least one processor of a computing device, to enable the at least one processor to: obtain an instruction sequence of an application program, wherein the instruction sequence comprises a plurality of instructions, the plurality of instructions comprise read/write instructions for performing at least one of a read operation or a write operation on one or more memories of the computing device, and the application program is deployed in the computing device; identify an execution sequence of the read/write instructions based on the instruction sequence; and execute the read/write instructions based on the execution sequence, wherein: the read/write instructions comprise at least one of a read instruction for performing the read operation on the one or more memories or a write instruction for performing the write operation on the one or more memories, the read instruction has a first semantic, and the write instruction has a second semantic, the first semantic indicates that a first instruction in the instruction sequence is executed after the read instruction is executed, wherein the first semantic prevents any instruction that is arranged after the read instruction in the instruction sequence from being executed before the read instruction is executed; and the second semantic indicates that a second instruction in the instruction sequence is executed before execution of the write instruction is completed, wherein the second semantic prevents any instruction that is arranged before the write instruction in the instruction sequence from being executed after the write instruction is executed, the read instruction is fetched through compiling an extended memory read instruction, the extended memory read instruction has the first semantic, and the extended memory read instruction is an instruction that is added to an instruction set of the at least one processor and that is used to instruct to read memory data; and the write instruction is fetched through compiling an extended memory write instruction, the extended memory write instruction has the second semantic, and the extended memory write instruction is an instruction that is added to the instruction set and that is used to instruct to write the memory data.
18. 18 . The non-transitory computer-readable storage medium of claim 17 , wherein the execution sequence of the read/write instructions is identified based on the instruction sequence by: identifying, in a sequential memory access mode, an arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions, wherein the sequential memory access mode requires that the execution sequence of the read/write instructions be consistent with the arrangement sequence of the read/write instructions in the instruction sequence.
19. 19 . The non-transitory computer-readable storage medium of claim 17 , wherein: for the first semantic, the first instruction is arranged after the read instruction in the instruction sequence; and for the second semantic, the second instruction is arranged before the write instruction in the instruction sequence.
20. 20 . The non-transitory computer-readable storage medium of claim 17 , wherein: the read/write instructions comprise a second read instruction that is fetched through compiling a second extended memory read instruction, and the second extended memory read instruction is an instruction fetched through adding the first semantic to a general memory read instruction in an instruction set of the at least one processor; and the read/write instructions comprise a second write instruction that is fetched through compiling a second extended memory write instruction, and the second extended memory write instruction is an instruction fetched through adding the second semantic to a general memory write instruction in the instruction set.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application No. PCT/CN2022/138259, filed on Dec. 11, 2022, which claims priority to Chinese Patent Application No. 202111506284.8, filed on Dec. 10, 2021, and Chinese Patent Application No. 202210238254.1 filed on Mar. 11, 2022. All of the aforementioned patent applications are hereby incorporated by reference in their entireties. TECHNICAL FIELD This application relates to the field of communication technologies, and in particular, to a data processing method, apparatus, and system, a computing device, and a storage medium. BACKGROUND An application program includes a read/write instruction for performing a read operation or a write operation on a memory. When executing the application program, a processor inevitably performs a read/write operation on the memory by executing the read/write instruction in the application program. However, in a process in which the processor performs the read/write operation on the memory, the processor may fail to normally execute the application program. SUMMARY This application provides a data processing method, apparatus, and system, a computing device, and a storage medium, so that a processor can normally run an application program. The technical solutions are as follows: According to a first aspect, a data processing method is provided. The method is performed by a processor of a computing device, and the method includes: obtaining an instruction sequence of an application program, identifying an execution sequence of read/write instructions in the instruction sequence based on the instruction sequence, and executing the read/write instructions based on the identified execution sequence, where the instruction sequence includes a plurality of instructions, the plurality of instructions include the read/write instructions for performing a read operation or a write operation on a memory of the computing device, and the application program is deployed in the computing device. In this method, the processor obtains the instruction sequence of the application program, identifies the execution sequence of the read/write instructions in the instruction sequence based on the instruction sequence, and executes the read/write instructions based on the identified execution sequence, to access the memory of the computing device, so that the processor can normally execute the application program. In a possible implementation, the identifying an execution sequence of read/write instructions in the instruction sequence based on the instruction sequence includes: identifying an arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions. Based on the foregoing possible implementation, the arrangement sequence of the read/write instructions in the instruction sequence is forcibly identified as the execution sequence of the read/write instructions, so that the arrangement sequence of the read/write instructions in the instruction sequence is consistent with the execution sequence of the read/write instructions. Correspondingly, when the processor executes the read/write instructions based on the execution sequence of the read/write instructions, a case in which a memory access order is inconsistent with the arrangement sequence of the read/write instructions in the application program can be avoided, so that a memory consistency problem can be avoided. In another possible implementation, the identifying an arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions includes: identifying, in a sequential memory access mode, the arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions, where the sequential memory access mode requires that the execution sequence of the read/write instructions be consistent with the arrangement sequence of the read/write instructions in the instruction sequence. Based on the foregoing possible implementation, the sequential memory access mode requires that the execution sequence of the read/write instructions be consistent with the arrangement sequence of the read/write instructions in the instruction sequence. Therefore, in the sequential memory access mode, the processor forcibly identifies the arrangement sequence of the read/write instructions in the instruction sequence as the execution sequence of the read/write instructions. Correspondingly, when the processor executes the read/write instructions based on the execution sequence of the read/write instructions, the case in which the memory access order is inconsistent with the arrangement sequence of the read/write instructions in the application program can be avoided, so that the memory consistency problem can be avoided. In another possible implementation, the read/write instructi