US-12625804-B2 - Flexible information compression at a memory system

Abstract

Methods, systems, and devices for flexible information compression at a memory system are described. For example, a memory system may compress information in a change log to reduce the frequency of transfers of one or more mappings between volatile memory and non-volatile memory. The memory system may compress information associated with a sequence of sequentially-indexed addresses by storing the information associated with those addresses at a pair of entries in the change log. The memory system may additionally switch between a first operating mode associated with identifying sequentially-indexed addresses and generating compressed entries, and a second operating mode associated with generating entries of the change log for each address received in commands.

Inventors

• Yanming Liu
• Zhenzhen Yang
• Yi Heng Sun
• Junjun Wang

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240517

Claims (20)

1. 1 . A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: generate, in response to a first command, a first entry of a change log with first information associated with a first logical address corresponding to the first command, the change log associated with a mapping between logical addresses and physical addresses of the memory system; receive a second command for accessing a second logical address associated with the memory system, the second logical address sequentially indexed with the first logical address; update, in accordance with a first mode of operation and the second logical address being sequentially indexed with the first logical address, the first entry of the change log with a first flag indicating that the first logical address is sequentially indexed with the second logical address, wherein the first mode of operation is associated with identifying sequentially-indexed addresses and generating compressed entries in the change log; and generate, in accordance with the first mode of operation, a second entry of the change log with second information associated with the second command, the second entry comprising a second flag indicating that the second logical address is sequentially indexed with the first logical address, wherein the second flag is separate from the first flag.
2. 2 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: determine that the second logical address is sequentially indexed with the first logical address; and transfer to the first mode of operation in response to the determination that the second logical address is sequentially indexed with the first logical address.
3. 3 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: transfer to a second mode of operation associated with generating entries of the change log for each address received in commands.
4. 4 . The memory system of claim 3 , wherein the processing circuitry is further configured to cause the memory system to: receive a third command for accessing a third logical address associated with the memory system; and generate, in accordance with the second mode of operation, a third entry of the change log with third information associated with the third command.
5. 5 . The memory system of claim 3 , wherein the processing circuitry is further configured to cause the memory system to: transfer to the second mode of operation in response to receiving a quantity of access commands including non-sequentially indexed addresses that exceeds a threshold value.
6. 6 . The memory system of claim 3 , wherein the processing circuitry is further configured to cause the memory system to: transfer to the second mode of operation in response to receiving one or more commands associated with accessing a sequence of random addresses.
7. 7 . The memory system of claim 3 , wherein the processing circuitry is further configured to cause the memory system to: receive a third command for accessing a third logical address associated with the memory system, wherein the third logical address is non-sequentially indexed with the first logical address and the second logical address; and increment a counter associated with identifying non-sequentially indexed addresses in response to the third logical address being non-sequentially indexed with the first logical address and the second logical address, wherein transferring to the second mode of operations is in response to the counter exceeding a threshold value.
8. 8 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a memory system, cause the memory system to: generate, in response to a first command, a first entry of a change log with first information associated with a first logical address corresponding to the first command, the change log associated with a mapping between logical addresses and physical addresses of the memory system; receive a second command for accessing a second logical address associated with the memory system, the second logical address sequentially indexed with the first logical address; update, in accordance with a first mode of operation and the second logical address being sequentially indexed with the first logical address, the first entry of the change log with a first flag indicating that the first logical address is sequentially indexed with the second logical address, wherein the first mode of operation is associated with identifying sequentially-indexed addresses and generating compressed entries in the change log; and generate, in accordance with the first mode of operation, a second entry of the change log with second information associated with the second command, the second entry comprising a second flag indicating that the second logical address is sequentially indexed with the first logical address, wherein the second flag is separate from the first flag.
9. 9 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: determine that the second logical address is sequentially indexed with the first logical address; and transfer to the first mode of operation in response to the determination that the second logical address is sequentially indexed with the first logical address.
10. 10 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: transfer to a second mode of operation associated with generating entries of the change log for each address received in commands.
11. 11 . The non-transitory computer-readable medium of claim 10 , wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: receive a third command for accessing a third logical address associated with the memory system; and generate, in accordance with the second mode of operation, a third entry of the change log with third information associated with the third command.
12. 12 . The non-transitory computer-readable medium of claim 10 , wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: transfer to the second mode of operation in response to receiving a quantity of access commands including non-sequentially indexed addresses that exceeds a threshold value.
13. 13 . The non-transitory computer-readable medium of claim 10 , wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: transfer to the second mode of operation in response to receiving one or more commands associated with accessing a sequence of random addresses.
14. 14 . The non-transitory computer-readable medium of claim 10 , wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: receive a third command for accessing a third logical address associated with the memory system, wherein the third logical address is non-sequentially indexed with the first logical address and the second logical address; and increment a counter associated with identifying non-sequentially indexed addresses in response to the third logical address being non-sequentially indexed with the first logical address and the second logical address, wherein transferring to the second mode of operations is in response to the counter exceeding a threshold value.
15. 15 . A method at a memory system, comprising: generating, in response to a first command, a first entry of a change log with first information associated with a first logical address corresponding to the first command, the change log associated with a mapping between logical addresses and physical addresses of the memory system; receiving a second command for accessing a second logical address associated with the memory system, the second logical address sequentially indexed with the first logical address; updating, in accordance with a first mode of operation and the second logical address being sequentially indexed with the first logical address, the first entry of the change log with a first flag indicating that the first logical address is sequentially indexed with the second logical address, wherein the first mode of operation is associated with identifying sequentially-indexed addresses and generating compressed entries in the change log; and generating, in accordance with the first mode of operation, a second entry of the change log with second information associated with the second command, the second entry comprising a second flag indicating that the second logical address is sequentially indexed with the first logical address, wherein the second flag is separate from the first flag.
16. 16 . The method of claim 15 , further comprising: determining that the second logical address is sequentially indexed with the first logical address; and transferring to the first mode of operation in response to the determination that the second logical address is sequentially indexed with the first logical address.
17. 17 . The method of claim 15 , further comprising: transferring to a second mode of operation associated with generating entries of the change log for each address received in commands.
18. 18 . The method of claim 17 , further comprising: receiving a third command for accessing a third logical address associated with the memory system; and generating, in accordance with the second mode of operation, a third entry of the change log with third information associated with the third command.
19. 19 . The method of claim 17 , further comprising: transferring to the second mode of operation in response to receiving a quantity of access commands including non-sequentially indexed addresses that exceeds a threshold value.
20. 20 . The method of claim 17 , further comprising: transferring to the second mode of operation in response to receiving one or more commands associated with accessing a sequence of random addresses.

Description

CROSS REFERENCE The present application for patent is a continuation of U.S. patent application Ser. No. 17/645,686 by Liu et al., entitled “FLEXIBLE INFORMATION COMPRESSION AT A MEMORY SYSTEM,” filed Dec. 22, 2021, which is assigned to the assignee hereof and is expressly incorporated by reference herein. FIELD OF TECHNOLOGY The following relates generally to one or more systems for memory and more specifically to flexible information compression at a memory system. BACKGROUND Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read, or sense, the state of one or more memory cells within the memory device. To store information, a component may write, or program, one or more memory cells within the memory device to corresponding states. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross point), not-or (NOR) and not-and (NAND) memory devices, and others. Memory devices may be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed states over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) may maintain their programmed states for extended periods of time even in the absence of an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a system that supports flexible information compression at a memory system in accordance with examples as disclosed herein. FIG. 2A illustrates an example of a change log that supports flexible information compression at a memory system in accordance with examples as disclosed herein. FIG. 2B illustrates an example of a change log compression scheme that supports flexible information compression at a memory system in accordance with examples as disclosed herein. FIG. 3 illustrates an example of a process flow that supports flexible information compression at a memory system in accordance with examples as disclosed herein. FIG. 4 shows a block diagram of a memory system that supports flexible information compression at a memory system in accordance with examples as disclosed herein. FIG. 5 shows a flowchart illustrating a method or methods that support flexible information compression at a memory system in accordance with examples as disclosed herein. DETAILED DESCRIPTION Memory devices of a memory system may store data at a physical address. For example, the memory system may receive a write command indicating data for the memory system to write in one or more memory devices. In some examples, a host device of the memory system may use a logical address as a reference to access the physical location of memory. For example, the write command may include a logical address (issued by the host system) associated with the data, which may be different than the physical address (issued by the memory system) used for storing the data. In some examples, the physical or logical location of data within a memory device may change over time due to the memory device accommodating the writing of additional data, maintenance operations performed by the memory device, or for other reasons. In some examples, a memory device may include a physical page table (PPT) to manage the mapping between logical addresses and physical addresses. For example, the PPT may be example of a logical-to-physical (L2P) mapping or table. The memory system may also use a page validity table (PVT) to indicate which physical addresses (e.g., pages) are presently storing valid information. In some examples, the PPT may be stored in non-volatile memory (e.g., NAND) but to update or change the PPT, portions of the PPT may be transferred to a volatile memory. In some cases, a change log may be stored in the volatile memory. The change log may record changes to the PPT (e.g., based on commands) so that changes to the PPT may be grouped and handled more efficiently. For the mapping between logical addresses and physical addresses to stay up to date, the memory device may periodically transfer update information from the temporary storage in volatile memory to the PPT in non-volatile storage (e.g., NAND). For example, if a host device sends a wr