US-12625805-B2 - Using a flag to indicate whether a mapping entry points to sequentially stored data

US12625805B2US 12625805 B2US12625805 B2US 12625805B2US-12625805-B2

Abstract

Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

Inventors

Giuseppe Cariello
Jonathan S. Parry

Assignees

LODESTAR LICENSING GROUP LLC

Dates

Publication Date: 20260512
Application Date: 20240903

Claims (20)

1 . An apparatus, comprising: one or more memory arrays; and one or more control components coupled with the one or more memory arrays and configured to cause the apparatus to: receive, from a host device, a plurality of write commands for writing data to the apparatus, the plurality of write commands comprising logical block addresses associated with a quantity of entries, the quantity of entries being for mapping a plurality of logical block addresses, comprising the logical block addresses, to a plurality of physical addresses, wherein the logical block addresses are consecutive; store, based at least in part on receiving the plurality of write commands, the data, in the apparatus, at a plurality of consecutive physical addresses, of the plurality of physical addresses, that starts with a first physical address; and store, based at least in part on a quantity of the logical block addresses matching the quantity of entries, both, the first physical address and a first value of a flag in a first entry of a plurality of entries.
2 . The apparatus of claim 1 , wherein a first logical block address of the logical block addresses corresponds to the first physical address, and wherein each of the logical block addresses corresponds to a respective consecutive physical address of the plurality of consecutive physical addresses.
3 . The apparatus of claim 1 , wherein the one or more control components are further configured to cause the apparatus to: store, for the plurality of write commands, one or more entries in a second plurality of entries of the quantity of entries, the second plurality of entries for mapping the logical block addresses to the plurality of consecutive physical addresses; and discard, based at least in part on determining that the quantity of the logical block addresses matches the quantity of entries, the second plurality of entries.
4 . The apparatus of claim 1 , wherein the one or more control components are further configured to cause the apparatus to: receive, from the host device after storing, both, the first physical address and the first value of the flag in the first entry of the plurality of entries, a read command comprising a third logical block address of the plurality of logical block addresses; read, based at least in part on receiving the read command, the first entry of the plurality of entries to read the first physical address and the first value of the flag; read, based at least in part on identifying a second physical address, a portion of the data from the second physical address, wherein identifying the second physical address is based at least in part on reading the first entry; and transmit the portion of the data to the host device.
5 . The apparatus of claim 1 , wherein the plurality of consecutive physical addresses are contained in a first block of the apparatus, and wherein the one or more control components are further configured to cause the apparatus to: receive, from the host device, a plurality of second write commands for writing second data to the apparatus, the one or more plurality of second write commands interleaved with the plurality of write commands, and the plurality of second write commands comprising second logical block addresses associated with a second quantity of entries, the second quantity of entries being for mapping a second plurality of logical block addresses, comprising the second logical block addresses, to a second plurality of physical addresses, wherein the second logical block addresses are consecutive; store, based at least in part on receiving the plurality of second write commands, the second data, in the apparatus, at a second plurality of consecutive physical addresses, of a second block, different than the first block, that is identified based at least in part on receiving the plurality of second write commands, the second plurality of consecutive physical addresses, being of the second plurality of physical addresses, that starts with a fourth physical address; and store, based at least in part on a second quantity of the second logical block addresses matching the second quantity of entries, both, the fourth physical address and the first value of a flag in a first entry of a second plurality of entries.
6 . The apparatus of claim 1 , wherein the one or more control components are further configured to cause the apparatus to: store an indication that a stream of data is open based at least in part on storing the data at the first physical address of the plurality of consecutive physical addresses, wherein storing the data at the plurality of consecutive physical addresses is based at least in part on determining that a first logical block address of the logical block addresses corresponds to the first entry of the quantity of entries.
7 . The apparatus of claim 6 , wherein the one or more control components are further configured to cause the apparatus to: receive, from the host device after receiving the plurality of write commands, a second write command comprising a third logical block address; and store a second indication that the stream of data is closed based at least in part on determining that a second physical address is not consecutive to the plurality of consecutive physical addresses.
8 . A non-transitory computer-readable medium storing code comprising instructions, which when executed by one or more processors of an electronic device, cause the electronic device to: receive, from a host device, a plurality of write commands for writing data to the electronic device, the plurality of write commands comprising logical block addresses associated with a quantity of entries, the quantity of entries being for mapping a plurality of logical block addresses, comprising the logical block addresses, to a plurality of physical addresses, wherein the logical block addresses are consecutive; store, based at least in part on receiving the plurality of write commands, the data, in the electronic device, at a plurality of consecutive physical addresses, of the plurality of physical addresses, that starts with a first physical address; and store, based at least in part on a quantity of the logical block addresses matching the quantity of entries, both, the first physical address and a first value of a flag in a first entry of a plurality of entries.
9 . The non-transitory computer-readable medium of claim 8 , wherein a first logical block address of the logical block addresses corresponds to the first physical address, and wherein each of the logical block addresses corresponds to a respective consecutive physical address of the plurality of consecutive physical addresses.
10 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: store, for the plurality of write commands, one or more entries in a second plurality of entries of the quantity of entries, the second plurality of entries for mapping the logical block addresses to the plurality of consecutive physical addresses; and discard, based at least in part on determining that the quantity of the logical block addresses matches the quantity of entries, the second plurality of entries.
11 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: receive, from the host device after storing, both, the first physical address and the first value of the flag in the first entry of the plurality of entries, a read command comprising a third logical block address of the plurality of logical block addresses; read, based at least in part on receiving the read command comprising the third logical block address, the first entry of the plurality of entries to read the first physical address and the first value of the flag; read, based at least in part on identifying a second physical address, a portion of the data from the second physical address, wherein identifying the second physical address is based at least in part on reading the first entry; and transmit the portion of the data to the host device.
12 . The non-transitory computer-readable medium of claim 8 , wherein the plurality of consecutive physical addresses are contained in a first block of the electronic device, and wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: receive, from the host device, a plurality of second write commands for writing second data to the electronic device, the plurality of second write commands interleaved with the plurality of write commands, and the plurality of second write commands comprising second logical block addresses associated with a second quantity of entries, the second quantity of entries being for mapping a second plurality of logical block addresses, comprising the second logical block addresses, to a second plurality of physical addresses; store, based at least in part on receiving the plurality of second write commands, the second data, in the electronic device, at a second plurality of consecutive physical addresses, of a second block, different than the first block, that is identified based at least in part on receiving the plurality of second write commands, the second plurality of consecutive physical addresses, being of the second plurality of physical addresses, that starts with a fourth physical address; and store, based at least in part on a second quantity of the second logical block addresses matching the second quantity of entries, both, the fourth physical address and the first value of a flag in a first entry of a second plurality of entries.
13 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: store an indication that a stream of data is open based at least in part on storing the data at the first physical address of the plurality of consecutive physical addresses, wherein storing the data at the plurality of consecutive physical addresses is based at least in part on determining that a first logical block address of the logical block addresses corresponds to the first entry of the quantity of entries.
14 . The non-transitory computer-readable medium of claim 13 , wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: receive, from the host device after receiving the plurality of write commands, a second write command comprising a third logical block address; and store a second indication that the stream of data is closed based at least in part on determining that a second physical address is not consecutive to the plurality of consecutive physical addresses.
15 . A method, comprising: receiving, from a host device, a plurality of write commands for writing data to an electronic device, the plurality of write commands comprising logical block addresses associated with a quantity of entries, the quantity of entries being for mapping a plurality of logical block addresses comprising the logical block addresses to a plurality of physical addresses, wherein the logical block addresses are consecutive; storing, based at least in part on receiving the plurality of write commands, the data, in the electronic device, at a plurality of consecutive physical addresses, of the plurality of physical addresses, that starts with a first physical address; and storing, based at least in part on a quantity of the logical block addresses matching the quantity of entries, both, the first physical address and a first value of a flag in a first entry of a plurality of entries.
16 . The method of claim 15 , wherein a first logical block address of the logical block addresses corresponds to the first physical address, and wherein each of the logical block addresses corresponds to a respective consecutive physical address of the plurality of consecutive physical addresses.
17 . The method of claim 15 , further comprising: storing, for the plurality of write commands, one or more entries in a second plurality of entries of the quantity of entries, the second plurality of entries for mapping the logical block addresses to the plurality of consecutive physical addresses; and discarding, based at least in part on determining that the quantity of the logical block addresses matches the quantity of entries, the second plurality of entries.
18 . The method of claim 15 , further comprising: receiving, from the host device after storing, both, the first physical address and the first value of the flag in the first entry of the plurality of entries, a read command comprising a third logical block address of the plurality of logical block addresses; reading, based at least in part on receiving the read command comprising the third logical block address, the first entry of the plurality of entries to read the first physical address and the first value of the flag; reading, based at least in part on identifying a second physical address, a portion of the data from the second physical address, wherein identifying the second physical address is based at least in part on reading the first entry; and transmitting the portion of the data to the host device.
19 . The method of claim 15 , wherein the plurality of consecutive physical addresses are contained in a first block of the electronic device, the method further comprising: receiving, from the host device, a plurality of second write commands for writing second data to the electronic device, the plurality of second write commands interleaved with the plurality of write commands, and the plurality of second write commands comprising second logical block addresses associated with a second quantity of entries, the second quantity of entries being for mapping a second plurality of logical block addresses, comprising the second logical block addresses, to a second plurality of physical addresses, wherein the second logical block addresses are consecutive; storing, based at least in part on receiving the plurality of second write commands, the second data, in the electronic device, at a second plurality of consecutive physical addresses, of a second block, different than the first block, that is identified based at least in part on receiving the plurality of second write commands, the second plurality of consecutive physical addresses, being of the second plurality of physical addresses, that starts with a fourth physical address; and storing, based at least in part on a second quantity of the second logical block addresses matching the second quantity of entries, both, the fourth physical address and the first value of a flag in a first entry of a second plurality of entries.
20 . The method of claim 15 , further comprising: storing an indication that a stream of data is open based at least in part on storing the data at the first physical address of the plurality of consecutive physical addresses, wherein storing the data at the plurality of consecutive physical addresses is based at least in part on determining that a first logical block address of the logical block addresses corresponds to the first entry of the quantity of entries.

Description

CROSS REFERENCE The present Application for Patent is a continuation of U.S. patent application Ser. No. 18/048,364 by Cariello et al., entitled “LOGICAL-TO-PHYSICAL MAPPING USING A FLAG TO INDICATE WHETHER A MAPPING ENTRY POINTS TO SEQUENTIALLY STORED DATA,” filed Oct. 20, 2022, which is a divisional of U.S. patent application Ser. No. 16/870,674 by Cariello et al., entitled “LOGICAL-TO-PHYSICAL MAPPING USING A FLAG TO INDICATE WHETHER A MAPPING ENTRY POINTS TO SEQUENTIALLY STORED DATA,” filed May 8, 2020, each of which is assigned to the assignee hereof, and each of which is expressly incorporated by reference herein. BACKGROUND The following relates generally to one or more memory systems and more specifically to compressed logical-to-physical mapping for sequentially stored data. Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. To access the stored information, a component may read, or sense, at least one stored state in the memory device. To store information, a component may write, or program, the state in the memory device. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D Xpoint), Flash memory (such as floating-gate Flash and charge-trapping Flash, which may be used in not- or (NOR) or not- and (NAND) memory devices), and others. Memory devices may be volatile or non-volatile. Non-volatile memory cells, such as flash memory cells, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory cells, such as DRAM cells, may lose their stored state over time unless they are periodically refreshed by an external power source. Flash-based memory devices may have different performance compared to other non-volatile and volatile memory devices. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a memory device that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. FIG. 2 illustrates an example of a NAND circuit that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. FIG. 3 illustrates an example of a system that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. FIG. 4 illustrates an example of an operational flow that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. FIG. 5 illustrates an example of an operational flow that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. FIG. 6 illustrates an example of a process that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. FIG. 7 shows a block diagram of a memory device that supports compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. FIGS. 8 and 9 show flowcharts illustrating a method or methods that support compressed logical-to-physical mapping for sequentially stored data in accordance with examples as disclosed herein. DETAILED DESCRIPTION A memory device, such as a device that includes Flash memory, among other examples, may be coupled with a host device and may receive commands, such as read and write commands for reading or writing data, from the host device. Flash memory is generally organized into pages and blocks, where each block may contain multiple pages. Flash memory cells may be read and written at a page level, but may be erased at a block level. In some examples, Flash memory cells may not be re-written without being erased first. Thus, when a Flash memory device updates a page of data (e.g., in response to a command from the host device), the memory device may write the new data to a different page and mark the old page as obsolete rather than erasing a block of memory and re-writing any valid pages in the block. For a write operation, the host device may refer to the location of data stored in the memory device using a logical block address (LBA) to identify a logical (e.g., conceptual) location of a page of data. The LBA may be mapped to a physical address of a page of memory of the memory device at which the data is stored. Because the physica