US-12625806-B2 - Apparatus and methods for statically mapping random write command data

Abstract

An apparatus includes a memory array including blocks of non-volatile memory cells and a control circuit coupled to the memory array. The control circuit is configured to receive first write commands, determine that the first write commands satisfy predetermined criteria, and process the first write commands by: statically mapping the logical block addresses to corresponding physical block addresses of first ones of the blocks of non-volatile memory cells, and writing data from the first write commands to the first ones of the blocks.

Inventors

• Abhinandan Venugopal
• Amit Sharma
• Sourabh Sankule

Assignees

• SanDisk Technologies, Inc.

Dates

Publication Date

20260512

Application Date

20241024

Claims (19)

1. 1 . An apparatus comprising: a memory array comprising blocks of non-volatile memory cells; and a control circuit coupled to the memory array, the control circuit configured to: receive a first plurality of write commands; determine that the first plurality of write commands satisfies predetermined criteria of only non-overlapping random write commands; process the first plurality of write commands that satisfies the predetermine criteria by: statically mapping the logical block addresses to corresponding physical block addresses of a first plurality of the blocks of non-volatile memory cells; and writing data from the first plurality of write commands to the first plurality of blocks.
2. 2 . The apparatus of claim 1 , wherein the first plurality of write commands comprise random write commands.
3. 3 . The apparatus of claim 1 , wherein each of the first plurality of write commands comprise less than a page of data.
4. 4 . The apparatus of claim 1 , wherein the control circuit is further configured to determine a range of logical block addresses in the first plurality of write commands.
5. 5 . The apparatus of claim 4 , wherein the control circuit is further configured to determine a number of a blocks needed to store data of the determined range of logical block addresses, wherein each block comprises memory cells configured to store one bit of data per memory cell.
6. 6 . The apparatus of claim 1 , wherein determining that the first plurality of write commands satisfies predetermined criteria comprises determining that the first plurality of write commands comprise non-repeating, non-overlapping write commands.
7. 7 . The apparatus of claim 1 , wherein the first plurality of the blocks comprise memory cells configured to store one bit of data per memory cell.
8. 8 . The apparatus of claim 1 , wherein the first plurality of the blocks comprise memory cells that may store more than one bit of data per memory cell, but the control circuit is configured to store only one bit of data per memory cell in the first plurality of the blocks.
9. 9 . The apparatus of claim 1 , wherein the control circuit is further configured to write data to the first plurality of blocks using partial page programming.
10. 10 . The apparatus of claim 1 , wherein the control circuit is further configured to write data to the first plurality of blocks using a one-to-one mapping of logical block addresses to corresponding block offsets.
11. 11 . The apparatus of claim 1 , wherein the control circuit is further configured to: receive a second plurality of write commands; determine that the second plurality of write commands does not satisfy the predetermined criteria; write data from the second plurality of write commands to sequential blocks of non-volatile memory cells; and create entries corresponding to the second plurality of write commands in a logical to physical address mapping table.
12. 12 . An apparatus comprising: a memory array comprising non-volatile memory cells; and a control circuit coupled to the memory array, the control circuit configured to: receive a plurality of random write commands of only non-overlapping random write commands; determine a range of logical block addresses in the random write commands; determine a number of a blocks needed to store data of the random write commands, wherein each block comprises memory cells configured to store one bit of data per memory cell; simultaneously open the determined number of blocks; statically map the logical block addresses to corresponding physical block addresses of the opened blocks of non-volatile memory cells; and write data from the random write commands to non-sequential flash management units in the opened blocks.
13. 13 . The apparatus of claim 12 , wherein the control circuit is further configured to prevent relocation of data in the opened blocks.
14. 14 . The apparatus of claim 12 , wherein the control circuit is further configured to close all of the opened blocks after completing writing data from the random write commands.
15. 15 . The apparatus of claim 14 , wherein the control circuit is further configured to allow relocation of data in the closed blocks.
16. 16 . The apparatus of claim 12 , wherein the plurality of random write commands comprise non-repeating, non-overlapping random write commands.
17. 17 . The apparatus of claim 12 , wherein the control circuit is further configured to write data to the opened blocks using partial page programming.
18. 18 . The apparatus of claim 12 , wherein the control circuit is further configured to write data from the random write commands to the memory array without updating a logical to physical address mapping table.
19. 19 . A method comprising: receiving a plurality of write commands at a control circuit coupled to a NAND memory array, each write command comprising a corresponding logical block address; determining that the plurality of write commands of only non-repeating, non-overlapping random write commands; determining a range of the corresponding logical block addresses of the plurality of write commands; simultaneously opening a plurality of blocks to store data of the plurality of write commands, each block comprising NAND memory cells each configured to store one bit of data; and writing the data of the plurality of write commands to the plurality of opened blocks using partial page programming, wherein the data are written without updating a logical to physical address map for the NAND memory array.

Description

BACKGROUND Memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, computing devices, and data servers. Memory may include nonvolatile memory or volatile memory. A nonvolatile memory allows information to be stored and retained even when the nonvolatile memory is not connected to a power source (e.g., a battery). Examples of nonvolatile memory include resistive random access memory (“ReRAM”), magnetoresistive random access memory (“MRAM”, ferroelectric random access memory (“FeRAM”), phase change memory (“PCM”), Selector-Only Memory (“SOM”), and the like. Input/output operations per second (“IOPS”) is a performance measurement used to characterize memory systems. Random IOPS (accessing locations on a storage device in a non-contiguous manner) is one benchmark commonly used to categorize memory systems. It is desirable for memory systems to have high random IOPS. For low cost non-volatile memory systems, however, achieving high random IOPS is difficult. BRIEF DESCRIPTION OF THE DRAWINGS Like-numbered elements refer to common components in the different figures. FIG. 1 is a block diagram of an embodiment of a memory system connected to a host. FIG. 2 is a block diagram of an embodiment of a Front End Processor Circuit. In some embodiments, the Front End Processor Circuit is part of a Controller. FIG. 3 is a block diagram of an embodiment of a Back End Processor Circuit. In some embodiments, the Back End Processor Circuit is part of a Controller. FIG. 4 is a block diagram of an embodiment of a memory package. FIG. 5A is a block diagram of one embodiment of a memory die. FIG. 5B is a block diagram of one embodiment of an integrated memory assembly. FIG. 5C depicts details of an individual sense block. FIGS. 6A and 6B depict different embodiments of integrated memory assemblies. FIG. 7A is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure. FIG. 7B is a block diagram of one embodiment of a memory structure having four planes. FIG. 7C depicts a top view of a portion of one embodiment of a block of memory cells. FIG. 7D depicts a cross sectional view of a portion of one embodiment of a block of memory cells. FIG. 7E depicts a cross sectional view of a portion of one embodiment of a block of memory cells. FIG. 7F is a cross sectional view of one embodiment of a vertical column of memory cells. FIG. 7G is a schematic of a plurality of NAND strings in multiple regions of a same block. FIGS. 8A-8D are diagrams each depicting example threshold voltage distributions. FIG. 9 is a flowchart describing an embodiment of a process for programming non-volatile memory. FIG. 10 depicts a word line voltage during programming and verify operations. FIG. 11 is a simplified diagram of a memory system connected to a host. FIG. 12 is a simplified diagram of a NAND-based memory system coupled to a host. FIG. 13 is a flow diagram depicting an example workload analysis process implemented by host write workload analyzer. FIG. 14 is a flow diagram depicting an example targeted write process. FIG. 15 is an example block depicting block offset values. FIG. 16 is a diagram depicting a mapping of an example host write workload. FIG. 17 is a flow diagram of a process for processing host random write commands. DETAILED DESCRIPTION Some non-volatile storage devices require low-cost implementations. To meet these requirements, memory controllers for such low-cost non-volatile storage devices typically are restricted to having a single processor, a limited amount of RAM, relatively low processing power, and no hardware acceleration or automation. Nevertheless, achieving high random IOPS is desirable, even in low-cost non-volatile storage devices. To address the above-described issues, a non-volatile storage device is proposed that includes a plurality of memory die, and a controller coupled to the plurality of memory die. The controller may be a low-cost controller (e.g., including a single processor, a limited amount of RAM, relatively low processing power, and no hardware automation) and is configured to selectively process host write commands that satisfy predetermined criteria. In an embodiment, the controller is configured to receive host write commands, and determine whether the write commands only include non-repeating, non-overlapping, random write commands. If so, in an embodiment the controller processes the host write commands by statically mapping a range of logical block addresses of the host write commands to corresponding physical block addresses of blocks of non-volatile memory cells that are configured to store one bit of data per memory cell. In an embodiment, the controller then writes data from the host write commands to the blocks using partial page programming and the static mapping, as described in more detail below. Without wanting to be bound by any particular theory, it is believed