US-12625807-B2 - Elastic configuration of data rate control parameters in a memory sub-system with single-level cell memory caching

Abstract

Processing logic in a memory sub-system monitors an amount of free space in a cache of a memory device, determines an operating gear of a host system based on the amount of free space in the cache of the memory device, and configures one or more data rate control parameters of the system based on the operating gear of the host system.

Inventors

• Paul Roger Stonelake
• Byron D. Harris
• Ramkumar Venkatachalam

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240731

Claims (20)

1. 1 . A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: monitoring an amount of free space in a cache of the memory device; determining an operating gear of a host system based on the amount of free space in the cache of the memory device; and configuring one or more data rate control parameters of the system based on the operating gear of the host system, wherein configuring the data rate control parameters comprises dynamically adjusting a target rate for data transfer operations during operation of the system.
2. 2 . The system of claim 1 , wherein the cache of the memory device comprises single-level-cell (SLC) memory.
3. 3 . The system of claim 1 , wherein determining the operating gear of the host system comprises comparing the amount of free space in the cache to respective threshold levels of free space corresponding to each of a plurality of operating gears.
4. 4 . The system of claim 3 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises configuring a rate at which data is migrated from the cache to a primary storage band of the memory device.
5. 5 . The system of claim 4 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises reducing the rate at which data is written from the host system to the cache of the memory device when the amount of free space in the cache is above a threshold level of free space.
6. 6 . The system of claim 3 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises configuring a rate at which data is written from the host system to the cache of the memory device.
7. 7 . The system of claim 6 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises reducing the rate at which data is written from the host system to the cache of the memory device when the amount of free space in the cache is below a threshold level of free space.
8. 8 . A method comprising: monitoring an amount of free space in a cache of a memory device; determining an operating gear of a host system based on the amount of free space in the cache of the memory device; and configuring one or more data rate control parameters of the system based on the operating gear of the host system, wherein configuring the data rate control parameters comprises dynamically adjusting a target rate for data transfer operations during operation of the system.
9. 9 . The method of claim 8 , wherein the cache of the memory device comprises single-level-cell (SLC) memory.
10. 10 . The method of claim 8 , wherein determining the operating gear of the host system comprises comparing the amount of free space in the cache to respective threshold levels of free space corresponding to each of a plurality of operating gears.
11. 11 . The method of claim 10 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises configuring a rate at which data is migrated from the cache to a primary storage band of the memory device.
12. 12 . The method of claim 11 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises reducing the rate at which data is written from the host system to the cache of the memory device when the amount of free space in the cache is above a threshold level of free space.
13. 13 . The method of claim 10 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises configuring a rate at which data is written from the host system to the cache of the memory device.
14. 14 . The method of claim 13 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises reducing the rate at which data is written from the host system to the cache of the memory device when the amount of free space in the cache is below a threshold level of free space.
15. 15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: monitoring an amount of free space in a cache of a memory device; determining an operating gear of a host system based on the amount of free space in the cache of the memory device; and configuring one or more data rate control parameters of the system based on the operating gear of the host system, wherein configuring the data rate control parameters comprises dynamically adjusting a target rate for data transfer operations during operation of the system.
16. 16 . The non-transitory computer-readable storage medium of claim 15 , wherein determining the operating gear of the host system comprises comparing the amount of free space in the cache to respective threshold levels of free space corresponding to each of a plurality of operating gears.
17. 17 . The non-transitory computer-readable storage medium of claim 16 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises configuring a rate at which data is migrated from the cache to a primary storage band of the memory device.
18. 18 . The non-transitory computer-readable storage medium of claim 17 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises reducing the rate at which data is written from the host system to the cache of the memory device when the amount of free space in the cache is above a threshold level of free space.
19. 19 . The non-transitory computer-readable storage medium of claim 16 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises configuring a rate at which data is written from the host system to the cache of the memory device.
20. 20 . The non-transitory computer-readable storage medium of claim 19 , wherein configuring the one or more data rate control parameters of the system based on the operating gear comprises reducing the rate at which data is written from the host system to the cache of the memory device when the amount of free space in the cache is below a threshold level of free space.

Description

TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to rate control in a memory sub-system with single-level cell memory caching. BACKGROUND A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 illustrates an example computing system that includes a memory sub-system in accordance with some embodiments of the present disclosure. FIG. 2 is a block diagram of an example structure of a memory device with single-level cell memory caching in accordance with embodiments of the present disclosure. FIG. 3 is a flow diagram of an example method of rate control in a memory sub-system with single-level cell memory caching in accordance with some embodiments of the present disclosure. FIG. 4 is a flow diagram of an example method of controlling a rate at which a host system writes data to a cache of a memory sub-system using the return of completion entries to the host system in accordance with some embodiments of the present disclosure. FIG. 5 is a block diagram illustrating a firmware queue storing completion entries for controlling a rate at which a host system writes data to a cache of a memory sub-system in accordance with some embodiments of the present disclosure. FIG. 6 is a flow diagram of an example method of elastic configuration of data rate control parameters in a memory sub-system in accordance with some embodiments of the present disclosure. FIG. 7 is a chart illustrating host operating gears for elastic configuration of data rate control parameters in a memory sub-system in accordance with some embodiments of the present disclosure. FIG. 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure are directed to rate control in a memory sub-system with single-level cell memory caching. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more dice, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. A memory device can be made up of bits arranged in a two-dimensional or a three-dimensional grid. Memory cells are formed onto a silicon wafer in an array of columns (also hereinafter referred to as bitlines) and rows (also hereinafter referred to as wordlines). A wordline can refer to one or more rows of memory cells of a memory device that are used with one or more bitlines to generate the address of each of the memory cells. The intersection of a bitline and wordline constitutes the address of the memory cell. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of the memory device in order to allow concurrent operations to take place on each plane. The memory device can include circuitry that performs concurrent memory page accesses of two or more memory planes. For example, the memory device can include multiple access line driver circuits and power circuits that can be shared by the planes of the memory device to facilitate concurrent access of pages of two or more memory planes, including different page types