US-12625809-B2 - Cache coherence shared state suppression

Abstract

A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

Inventors

• Abhijeet Ashok Chachad
• David Matthew Thompson
• Timothy David Anderson
• Kai Chirca

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260512

Application Date

20240924

Claims (20)

1. 1 . A device, comprising: a cache memory; and a cache controller associated with the cache memory and configured to: store a value that specifies whether the cache controller is configured to operate in a first mode or a second mode, wherein a first coherence state is supported in the first mode and not supported in the second mode; receive a first cache request associated with the first coherence state; and determine whether to generate, in response to the first cache request, a second cache request associated with the first coherence state or associated with a second coherence state based on the value.
2. 2 . The device of claim 1 , wherein the first coherence state is a shared state.
3. 3 . The device of claim 2 , wherein the second coherence state is an exclusive state.
4. 4 . The device of claim 2 , wherein the second coherence state is an invalid state.
5. 5 . The device of claim 2 , wherein: the first cache request is an allocating read request; and the second cache request is a read without snoop request.
6. 6 . The device of claim 2 , wherein: the first cache request is a non-allocating read request; and the second cache request is a read without snoop request.
7. 7 . The device of claim 2 , wherein: the first cache request is a coherent allocating read request; and the second cache request is a read exclusive request.
8. 8 . The device of claim 2 , wherein: the first cache request is a coherent non-allocating read request; and the second cache request is a read once request.
9. 9 . The device of claim 1 , wherein: the cache memory is a level-two (L2) cache memory, and the cache controller is an L2 cache controller; the device further comprises a level-one (L1) cache memory and an L1 cache controller; and the L2 cache controller is configured to receive the first cache request from the L1 cache request.
10. 10 . The device of claim 1 , wherein: the first cache request is a first snoop request; and the second cache request is a second snoop request.
11. 11 . The device of claim 10 , wherein: the cache memory is a level-two (L2) cache memory, and the cache controller is an L2 cache controller; the device further comprises a level-three (L3) cache memory and an L3 cache controller; and the L2 cache controller is configured to receive the first cache request from the L3 cache request.
12. 12 . The device of claim 11 , wherein: the device further comprises a level-one (L1) cache memory and an L1 cache controller; and the L2 cache controller is configured to provide the second cache request to the L1 cache controller.
13. 13 . A method, comprising: storing, by a cache controller, a value that specifies whether the cache controller is configured to operate in a first mode or a second mode, wherein a first coherence state is supported in the first mode and not supported in the second mode; receiving, by the cache controller, a first cache request associated with the first coherence state; and determining, by the cache controller, whether to generate, in response to the first cache request, a second cache request associated with the first coherence state or associated with a second coherence state based on the value.
14. 14 . The method of claim 13 , wherein the first coherence state is a shared state.
15. 15 . The method of claim 14 , wherein the second coherence state is an exclusive state.
16. 16 . The method of claim 14 , wherein the second coherence state is an invalid state.
17. 17 . The method of claim 14 , wherein: the first cache request is an allocating read request; and the second cache request is a read without snoop request.
18. 18 . The method of claim 14 , wherein: the first cache request is a non-allocating read request; and the second cache request is a read without snoop request.
19. 19 . The method of claim 14 , wherein: the first cache request is a coherent allocating read request; and the second cache request is a read exclusive request.
20. 20 . The method of claim 14 , wherein: the first cache request is a coherent non-allocating read request; and the second cache request is a read once request.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation of U.S. patent application Ser. No. 18/325,190, filed May 30, 2023, which is a continuation of U.S. Patent application No. 17/666,196, filed Feb. 7, 2022, now U.S. Pat. No. 11,675,700, issued Jun. 13, 2023, which is a continuation of U.S. patent application Ser. No. 16/882,257, filed May 22, 2020, now U.S. Pat. No. 11,243,883, issued Feb. 8, 2022, which claims priority to U.S. Provisional Patent Application No. 62/852,416, filed May 24, 2019, each of which is incorporated by reference herein in its entirety. BACKGROUND Some memory systems include a multi-level cache system, in which a hierarchy of memories (e.g., caches) provides varying access speeds to cache data. A first level (L1) cache is closely coupled to a central processing unit (CPU) core and provides the CPU core with relatively fast access to cache data. A second level (L2) cache is also coupled to the CPU core and, in some examples, is larger and thus holds more data than the L1 cache, although the L2 cache provides relatively slower access to cache data than the L1 cache. Additional memory levels of the hierarchy are possible. SUMMARY In accordance with at least one example of the disclosure, a method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache. In accordance with at least one example of the disclosure, an apparatus, includes a central processing unit (CPU) core and a level one (L1) cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache and a L1 controller. The L1 controller is configured to determine to change a size of the L1 main cache, service pending read requests and pending write requests from the CPU core, stall new read requests and new write requests from the CPU core, and write back and invalidate the L1 main cache. The apparatus also includes a level two (L2) cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, and a L2 controller. The L2 controller is configured to receive an indication that the L1 main cache has been invalidated and, in response, flush a pipeline of the L2 controller; in response to the pipeline being flushed, stall requests received from any master; and reinitialize the shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache. In accordance with another example of the disclosure, a method includes receiving, by a level two (L2) controller, an indication that the a level one (L1) main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; and reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache. In accordance with at least one example of the disclosure, an apparatus includes a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache. In accordance with at least one example of the disclosure, a method includes receiving, by a level two (L2) controller of a L2 cache subsystem, an indication from a level one (L1) cache subsystem that a cache line A is being relocated from a L1 main cache to a L1 victim cache; in response to the indication, updating, by the L