US-12625812-B2 - Coherent system and a method of maintaining cache coherence using thereof

US12625812B2US 12625812 B2US12625812 B2US 12625812B2US-12625812-B2

Abstract

A coherent system including a plurality of processing units; an interconnect comprising a snoop filter, a conflict buffer to track in-progress or outstanding snoop, and a snoop state machine for managing snoop requests and snoop responses between the snoop filter, the conflict buffer and the processing units; wherein the snoop filter is configured to copy cacheline data of a cacheline that the processing unit reads on, match the cacheline address with tags of the snoop filter, and receive the snoop responses; wherein the conflict buffer is configured to indicate a hit or miss status based on the matching of the snoop filter and to send peer-cache snoop requests to different processing units. Further, a method of maintaining cache coherence using the coherent system also disclosed.

Inventors

Soon Chieh Lim
Yu Ying Ong

Assignees

SKYECHIP BERHAD

Dates

Publication Date: 20260512
Application Date: 20240916
Priority Date: 20240208

Claims (7)

1 . A method of maintaining cache coherence using a coherent system, the method comprising: providing a coherent system including a plurality of processing units, and an interconnect comprising a snoop filter, a conflict buffer to track in-progress or outstanding snoop, and a snoop state machine for managing snoop requests and snoop responses between the snoop filter, the conflict buffer and the plurality of processing units, wherein the snoop filter is configured to copy cacheline data of a cacheline that the plurality of processing units read on, match an address of the cacheline with tags of the snoop filter, and receive the snoop responses, wherein the conflict buffer is configured to indicate a hit or miss status based on matching of the snoop filter and to send peer-cache snoop requests to different processing units of the plurality of processing units; sending a snoop query by a snoop state machine to a snoop filter when a processing unit reads a cacheline; matching a query address of the snoop filter with the address of the cacheline; comparing the address of the cacheline with all tags of the snoop filter; indicating a miss result in the snoop filter if the tags are not matched; choosing a set of the snoop filter to pass the miss result to the snoop state machine; searching a snoop ID in a conflict buffer that has a fewer number of entries than the snoop filter, if no entry matched, selecting a free entry in the conflict buffer, marking a snoop ID of the selected free entry of the conflict buffer with a value of the query address and set an in-progress bits of that entry of the conflict buffer to 1 that it indicates that the snoop query for the query address is now in progress; sending a query to a subsequent cacheline by a subsequent processing unit; and repeating comparing address of the subsequent cacheline with all tags of the snoop filter to find a match.
2 . The method of claim 1 , wherein for an area-saving mode, sending snoop requests by the snoop state machine to other processing units to snoop for any processing units that contain a same cacheline while searching the snoop ID in the conflict buffer for a miss result.
3 . The method of claim 1 , further comprising hitting the snoop filter having the tag matched with the address of the cacheline when the processing unit requests a repeated cacheline, to enable snoop request sending by the processing unit.
4 . The method of claim 1 , wherein the method further comprises: postponing snoop requests to other processing units when the in-progress bits of an entry of the conflict buffer is all 1, where a snoop query address is equal to the snoop ID of that entry of the conflict buffer; updating an entry of the snoop filter with information of the processing unit and its ownership of the cacheline; clearing one of the in-progress bits to 0; retrying the snoop request to a new cacheline; updating a same entry of the snoop filter with information of subsequent processing units and subsequent cachelines; and clearing the in-progress bits to all 0.
5 . The method of claim 4 , wherein an entry of the conflict buffer is free to track other entries of the snoop filter when the in-progress bits are all 0.
6 . The method of claim 1 , wherein for a high-performance mode, further comprising updating the processing unit with an exclusive ownership of the respective cacheline.
7 . The method of claim 6 , wherein performing a snoop invalidation request to the processing unit to release the exclusive ownership of the respective cacheline when the snoop filter of a used entry receives a miss result for a new cacheline, and updating the exclusive ownership of the new cacheline.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of Malaysian Patent Application No. PI2024000899 filed in the Malaysian Intellectual Property Office on Feb. 8, 2024, the entire contents of which are incorporated herein by reference its entirety. TECHNICAL FIELD The present invention relates generally to a cache-coherent Network-On-Chip (NoC) architecture. More particularly, the present invention relates to a coherent system implemented with snoop filter and a method of maintaining cache coherence using the coherent system. BACKGROUND ART A snoop filter is basically a directory that keeps track of which central processing unit in a coherent system has a copy of the cacheline. The snoop filter is an array of multiple entries. It is essentially organized just like a cache. The array can be arranged in a direct-mapped style or a set-associate style, similar to a data cache. In a normal cache, the entire cacheline is stored as data. Traditionally, static random access memory is used for 1:1 mapping of valid and in-progress status bits to each snoop filter entry, which requires a large area for implementation and restricts to the network bandwidth capacity. There have been several solutions provided to improve coherent system and a method of maintaining cache coherence using a coherent system, and one of them has been discussed below: US20160062890 A1 related to an interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. The aforementioned reference provides an interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. Nevertheless, it still has a number of limitation and shortcoming such as non-scalable, consuming large area for implementation and inflexible Accordingly, there remains a need to provide a scalable coherent system and method to maintaining cache coherence using the coherent system for area saving and better performance. SUMMARY OF THE INVENTION The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. It is an objective of the present invention to provide a dual mode snoop filter with conflict buffer for an area-efficient and flexible implementation that can be easily scaled according to system requirements. Accordingly, these objectives may be achieved by following the teachings of the present invention. The present invention relates to a coherent system, characterized by: a plurality of processing units; an interconnect comprising a snoop filter, a conflict buffer to track in-progress or outstanding snoop, and a snoop state machine for managing snoop requests and snoop responses between the snoop filter, the conflict buffer and the processing units; wherein the snoop filter is configured to copy cacheline data of the cacheline that the processing unit reads on, match the cacheline address with tags of the snoop filter, and receive the snoop responses; wherein the conflict buffer is configured to indicate a hit or miss status based on the matching of the snoop filter and to send peer-cache snoop requests to different processing units. The present invention also relates to a method of maintaining cache coherence using a coherent system, the method comprising the steps of: sending a query by a snoop state machine to a snoop filter when a processing unit reads a cacheline; matching the query address of the snoop filter with the address of the cacheline; comparing address of the cacheline with all tags of the snoop filter; indicating a miss result in the snoop filter if the tags are not matched; choosing a set of the snoop filter to pass the miss result to the snoop state machine; searching a snoop ID in a conflict buffer that has a fewer number of entries than the snoop filter, if no entry matched, selecting a free entry in the conflict buffer, marking the snoop ID of the selected free entry of the conflict buffer with the value of the query address and set an in-pr