US-12625815-B2 - Memory pipeline control in a hierarchical memory system

Abstract

In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Inventors

• Abhijeet Ashok Chachad
• Timothy Anderson
• Kai Chirca
• David Matthew Thompson

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260512

Application Date

20241211

Claims (20)

1. 1 . A system, comprising: a cache memory; and a first cache controller comprising: a pipeline associated with the cache memory; and a bypass path configured to bypass the pipeline, wherein the first cache controller is configured to: receive a first transaction; determine whether to enter a bypass mode; and based on a determination to enter the bypass mode, provide the first transaction to a second cache controller via the bypass path; determine whether a next transaction is a bypass write transaction; and based on a determination that the next transaction is a bypass write transaction, remain in the bypass mode to provide the next transaction to the second cache controller via the bypass path.
2. 2 . The system of claim 1 , wherein to determine whether to enter the bypass mode, the first cache controller is configured to determine whether a transaction inhibiting use of the bypass path for the first transaction exists in the pipeline.
3. 3 . The system of claim 2 , wherein to determine whether to enter the bypass mode, the first cache controller is further configured to determine whether the first transaction is a bypass write transaction.
4. 4 . The system of claim 3 , wherein the first cache controller is configured to determine whether the first transaction is a bypass write transaction based on a determination whether the first transaction specifies a write of data to the cache memory.
5. 5 . The system of claim 4 , wherein the first cache controller is configured to determine whether the first transaction specifies a write of data to the cache memory based on a data payload size associated with the first transaction.
6. 6 . The system of claim 2 , wherein to remain in the bypass mode, the first cache controller is configured to send the next transaction to the second cache controller via the bypass path without determining whether a transaction inhibiting use of the bypass path for the next transaction exists in the pipeline.
7. 7 . The system of claim 2 , wherein: the cache memory is a level-two (L2) cache memory; the first cache controller is a level-two (L2) cache controller; and the second cache controller is a level-three (L3) cache controller.
8. 8 . The system of claim 7 , wherein the transaction inhibiting use of the bypass path is a write associated with a level-one (L1) cache.
9. 9 . The system of claim 1 , wherein the first cache controller is configured to: based on a determination to not enter the bypass mode, provide the first transaction to the pipeline rather than providing the first transaction to the second cache controller via the bypass path.
10. 10 . The system of claim 1 , wherein the first cache controller is configured to: based on a determination that the next transaction is not a bypass write transaction, exit the bypass mode to provide the next transaction to the pipeline rather than providing the next transaction to the second cache controller via the bypass path.
11. 11 . A method, comprising: receiving, at a first cache controller, a first transaction, wherein the first cache controller comprises a pipeline associated with a cache memory and a bypass path that bypasses the pipeline; determining, using the first cache controller, whether to enter a bypass mode; and based on determining to enter the bypass mode, providing, using the first cache controller, the first transaction to a second cache controller via the bypass path; determining, using the first cache controller, whether a next transaction is a bypass write transaction; and based on determining that the next transaction is a bypass write transaction, remaining in the bypass mode to provide the next transaction to the second cache controller via the bypass path.
12. 12 . The method of claim 11 , wherein determining whether to enter the bypass mode comprises determining whether a transaction inhibiting use of the bypass path for the first transaction exists in the pipeline.
13. 13 . The method of claim 12 , wherein determining whether to enter the bypass mode further comprises determining whether the first transaction is a bypass write transaction.
14. 14 . The method of claim 13 , wherein determine whether the first transaction is a bypass write transaction is performed based on determining whether the first transaction specifies a write of data to the cache memory.
15. 15 . The method of claim 14 , wherein determining whether the first transaction specifies a write of data to the cache memory is performed based on a data payload size associated with the first transaction.
16. 16 . The method of claim 12 , wherein remaining in the bypass mode comprises providing the next transaction to the second cache controller via the bypass path without determining whether a transaction inhibiting use of the bypass path for the next transaction exists in the pipeline.
17. 17 . The method of claim 12 , wherein: the cache memory is a level-two (L2) cache memory; the first cache controller is a level-two (L2) cache controller; and the second cache controller is a level-three (L3) cache controller.
18. 18 . The method of claim 17 , wherein the transaction inhibiting use of the bypass path is a write transaction associated with a level-one (L1) cache.
19. 19 . The method of claim 11 , comprising: receiving, at the first cache controller, a second transaction; determining, using the first cache controller, whether to enter the bypass mode; and based on determining to not enter the bypass mode, providing the second transaction to the pipeline rather than providing the second transaction to the second cache controller via the bypass path.
20. 20 . The method of claim 11 , comprising: receiving, at the first cache controller, a second transaction; determining, using the first cache controller, whether to enter the bypass mode; and based on determining to enter the bypass mode, providing, using the first cache controller, the second transaction to the second cache controller via the bypass path; determining, using the first cache controller, whether a next transaction of the second transaction is a bypass write transaction; and based on determining that the next transaction of the second transaction is not a bypass write, exiting the bypass mode to provide the next transaction of the second transaction to the pipeline rather than providing the next transaction of the second transaction to the second cache controller via the bypass path.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of and claims priority to U.S. patent application Ser. No. 18/584,181, filed Feb. 22, 2024, which is a continuation of U.S. patent application Ser. No. 18/167,921, filed Feb. 13, 2023, now U.S. Pat. No. 11,940,918, issued Mar. 26, 2024, which is a continuation of U.S. patent application Ser. No. 17/492,776, filed Oct. 4, 2021, now U.S. Pat. No. 11,580,024, issued on Feb. 14, 2023, which is a continuation of U.S. patent application Ser. No. 16/879,264, filed May 20, 2020, now U.S. Pat. No. 11,138,117, issued Oct. 5, 2021, which claims priority to U.S. Provisional Patent Application No. 62/852,480, filed May 24, 2019, all of which are hereby incorporated herein by reference in their entireties. TECHNICAL FIELD The present disclosure relates generally to a processing device that can be formed as part of an integrated circuit, such as a system on a chip (SoC). More specifically, this disclosure relates to such a system with improved management of write operations. BACKGROUND An SOC is an integrated circuit with multiple functional blocks (such as one or more processor cores, memory, and input and output) on a single die. Hierarchical memory moves data and instructions between memory blocks with different read/write response times for respective processor cores, such as a central processing unit (CPU) or a digital signal processor (DSP). For example, memories which are more local to respective processor cores will typically have lower response times. Hierarchical memories include cache memory systems with multiple levels (such as L1 and L2), in which different levels describe different degrees of locality or different average response times of the cache memories to respective processor cores. Herein, the more local or lower response time cache memory (such as an L1 cache) is referred to as being a higher level cache memory than a less local or higher response time lower level cache memory (such as an L2 cache or L3 cache). Associativity of a cache refers to the cache storage segregation, where set associativity divides the cache into a number of storage sets and each such set stores a number (the way) of blocks, while a fully associative cache is unconstrained by a set limitation. Accordingly, for an integer N, each location in main memory (system memory) can reside in any one of N possible locations in an N-way associative cache. A “victim cache” memory caches data (such as a cache line) that was evicted from a cache memory, such as an L1 cache. If an L1 cache read results in a miss (the data corresponding to a portion of main memory is not stored in the L1 cache), then a lookup occurs in the victim cache. If the victim cache lookup results in a hit (the data corresponding to the requested memory address is present in the victim cache), the contents of the victim cache location producing the hit, and the contents of a corresponding location in the respective cache (L1 cache in this example), are swapped. Some example victim caches are fully associative. Data corresponding to any location in main memory can be mapped to (stored in) any location in a fully associative cache. SUMMARY In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example processor that is a portion of an SoC. FIG. 2 is a block diagram of an example memory pipeline for the SoC of FIG. 1. FIG. 3 is an example of a process for memory write operations for the SoC of FIG. 1. FIG. 4 is a block diagram of an example memory pipeline for the SoC of FIG. 1. FIG. 5 is an example of a process for memory write operations for the SoC of FIG. 1. DETAILED DESCRIPTION FIG. 1 is a block diagram of an example processor 100 that is a portion of an SoC 10. SoC 10 includes a processor core 102, such as a CPU or DSP, that generates new data. Processor 100 can include a clock 103, which can be part of processor core 102 or separate therefrom (separate clock not shown). Processor core 102 also generates memory read requests that request reads from, as well as memory write requests that reque