US-12625824-B2 - Computer system and mode switching method thereof

US12625824B2US 12625824 B2US12625824 B2US 12625824B2US-12625824-B2

Abstract

A computer system and a mode switching method thereof are provided. The computer system includes a processor, a plurality of peripheral components, and a switch. The switch is coupled to the processor via a first transmission interface link and respectively coupled to the plurality of peripheral components via second transmission interface links. The switch includes a first flag register and a second flag register. When a first target peripheral component in the peripheral components is to be entered into a low power consumption mode, the processor sets a low power consumption flag bit corresponding to the first target peripheral component in the first flag register. When a second target peripheral component in the low power consumption mode in the peripheral components transmits a wake-up signal to the switch, the switch sets a wake-up flag bit corresponding to the second target peripheral component in the second flag register.

Inventors

Chunyuan Su
Ming-Han Hsu

Assignees

ASMEDIA TECHNOLOGY INC.

Dates

Publication Date: 20260512
Application Date: 20240728
Priority Date: 20240710

Claims (18)

1 . A computer system, comprising: a processor; a plurality of peripheral components; and a switch coupled to the processor via a first transmission interface link and respectively coupled to the peripheral components via a plurality of second transmission interface links, wherein the switch comprises a first flag register and a second flag register, when a first target peripheral component in the peripheral components is to be entered into a low power consumption mode, the processor sets a low power consumption flag bit corresponding to the first target peripheral component in the first flag register, when a second target peripheral component in the low power consumption mode in the peripheral components transmits a wake-up signal to the switch, the switch sets a wake-up flag bit corresponding to the second target peripheral component in the second flag register, wherein when the low power consumption flag bit corresponding to the first target peripheral component is set, a handshake operation is performed between the switch and the first target peripheral component, and the processor makes the second transmission interface link between the switch and the first target peripheral component enter a low power consumption state.
2 . The computer system of claim 1 , further comprising: a memory coupled to the processor and configured to store a basic input and output system program module, the processor loads the basic input and output system program module to perform a power management.
3 . The computer system of claim 1 , wherein the switch transmits a turn-off signal to the first target peripheral component and waits for the first target peripheral component to return an acknowledge signal.
4 . The computer system of claim 1 , wherein after the handshake operation is completed, the second transmission interface link between the switch and the first target peripheral component is switched to a ready state, and then the processor makes the second transmission interface link between the switch and the first target peripheral component enter the low power consumption state.
5 . The computer system of claim 1 , wherein after the second transmission interface link between the switch and the first target peripheral component enters the low power consumption state, the switch clears the low power consumption flag bit corresponding to the first target peripheral component.
6 . The computer system of claim 1 , wherein the switch further comprises: a power enable controller configured to stop providing a power to the first target peripheral component after the second transmission interface link between the switch and the first target peripheral component enters the low power consumption state; a reset controller configured to keep the first target peripheral component reset after the second transmission interface link between the switch and the first target peripheral component enters the low power consumption state; and a clock controller configured to stop providing a clock signal to the first target peripheral component after the second transmission interface link between the switch and the first target peripheral component enters the low power consumption state.
7 . The computer system of claim 1 , wherein when the second target peripheral component in the low power consumption mode in the peripheral components transmits the wake-up signal to the switch, the switch also transmits an input and output signal to the processor via a general-purpose input and output pin.
8 . The computer system of claim 7 , wherein when the processor receives the input and output signal, the second flag register is detected to learn about the second target peripheral component transmitting the wake-up signal, and then clears the wake-up flag bit corresponding to the second target peripheral component.
9 . The computer system of claim 8 , wherein the switch further comprises: a power enable controller configured to resume providing a power to the second target peripheral component after the processor learns that the second target peripheral component transmitting the wake-up signal is received; a reset controller configured to release a reset of the second target peripheral component after the processor learns that the second target peripheral component transmitting the wake-up signal is received; and a clock controller configured to resume providing a clock signal to the second target peripheral component after the processor learns that the second target peripheral component transmitting the wake-up signal is received.
10 . A mode switching method, adapted for a computer system comprising a plurality of peripheral components and a switch, wherein the switch is respectively coupled to the peripheral components via a plurality of transmission interface links and comprises a first flag register and a second flag register, and the mode switching method comprises the following steps: setting a low power consumption flag bit corresponding to a first target peripheral component in the peripheral components in the first flag register when the first target peripheral component is to be entered into a low power consumption mode; setting a wake-up flag bit corresponding to a second target peripheral component in the peripheral components in the second flag register when the second target peripheral component in the low power consumption mode transmits a wake-up signal to the switch; and performing a handshake operation between the switch and the first target peripheral component and making the transmission interface link between the switch and the first target peripheral component enter a low power consumption state when the low power consumption flag bit corresponding to the first target peripheral component is set.
11 . The mode switching method of claim 10 , further comprising: loading a basic input and output system program module to perform a power management.
12 . The mode switching method of claim 10 , wherein the step of performing the handshake operation between the switch and the first target peripheral component comprises: transmitting a turn-off signal to the first target peripheral component via the switch, and waiting for the first target peripheral component to return an acknowledge signal.
13 . The mode switching method of claim 10 , wherein the step of making the transmission interface link between the switch and the first target peripheral component enter the low power consumption state further comprises: switching the transmission interface link between the switch and the first target peripheral component to a ready state, and then making the transmission interface link between the switch and the first target peripheral component enter the low power consumption state after the handshake operation is completed.
14 . The mode switching method of claim 10 , further comprising, after the step of making the transmission interface link between the switch and the first target peripheral component enter the low power consumption state: clearing the low power consumption flag bit corresponding to the first target peripheral component.
15 . The mode switching method of claim 10 , further comprising, after the step of making the transmission interface link between the switch and the first target peripheral component enter the low power consumption state: stopping providing a power to the first target peripheral component; keeping the first target peripheral component reset; and stopping providing a clock signal to the first target peripheral component.
16 . The mode switching method of claim 10 , further comprising: transmitting an input and output signal via a general-purpose input and output pin when the second target peripheral component in the low power consumption mode in the peripheral components transmits the wake-up signal to the switch.
17 . The mode switching method of claim 16 , further comprising: detecting the second flag register to learn about the second target peripheral component transmitting the wake-up signal when the input and output signal is received, and then clearing the wake-up flag bit corresponding to the second target peripheral component.
18 . The mode switching method of claim 17 , further comprising, after the step of learning about the second target peripheral component transmitting the wake-up signal: resuming providing a power to the second target peripheral component; releasing a reset of the second target peripheral component; and resuming providing a clock signal to the second target peripheral component.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of Taiwan application serial no. 113125832, filed on Jul. 10, 2024. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND OF THE INVENTION Field of the Invention The invention relates to a computer system, and in particular, to a computer system capable of entering a low power consumption mode and a mode switching method adopted thereby. Description of Related Art The Peripheral Component Interconnect Express (PCIe) bus is an industry-standard computer expansion technique developed by the PCI Special Interest Group (PCI-SIG). According to the standards currently published by PCI-SIG, peripheral components or devices under the PCIe switch may not individually enter low power consumption mode (for example, the D3 mode specified by Advanced Configuration and Power Interface (ACPI)). Therefore, it is currently only possible to achieve the situation in which all peripheral components or devices under the PCIe switch enter the low power consumption mode at the same time. In addition, once one of the peripheral components or devices is to return to the operating mode (for example, the D0 mode specified by ACPI), all peripheral components or devices under the PCIe switch also need to return to the D0 mode. This behavior of entering and exiting at the same time may not achieve effective power saving, thus resulting in poor power saving effect and causing the issue of excessive power consumption. SUMMARY OF THE INVENTION The invention provides a computer system and a mode switching method thereof that may allow peripheral components under a PCIe switch to individually enter a low power consumption mode. A computer system of the invention includes a processor, a plurality of peripheral components, and a switch. The switch is coupled to the processor via a first transmission interface link and respectively coupled to the plurality of peripheral components via second transmission interface links. The switch includes a first flag register and a second flag register. When a first target peripheral component in the peripheral components is to be entered into a low power consumption mode, the processor sets a low power consumption flag bit corresponding to the first target peripheral component in the first flag register. When a second target peripheral component in the low power consumption mode in the peripheral components transmits a wake-up signal to the switch, the switch sets a wake-up flag bit corresponding to the second target peripheral component in the second flag register. A mode switching method of the invention is suitable for a computer system including a plurality of peripheral components and a switch. The switch is respectively coupled to the plurality of peripheral components via a plurality of transmission interface connection links, and includes a first flag register and a second flag register. The mode switching method includes the following steps: setting a low power consumption flag bit corresponding to a first target peripheral component in the peripheral components in the first flag register when the first target peripheral component is to be entered into a low power consumption mode; and setting a wake-up flag bit corresponding to a second target peripheral component in the peripheral components in the second flag register when the second target peripheral component in the low power consumption mode transmits a wake-up signal to the switch. Based on the above, the computer system and the mode switching method thereof of the invention may allow peripheral components under the switch to individually enter the low power consumption mode by setting a specially configured flag register. In this way, the power saving mechanism may be made more flexible, power saving efficiency may be improved, and therefore the issue of excessive power consumption may be solved. In order to make the aforementioned features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a computer system shown according to an embodiment of the invention. FIG. 2 is a flowchart of a mode switching method shown according to an embodiment of the invention. FIG. 3 is a flowchart of a mode switching method shown according to an embodiment of the invention. FIG. 4 is a flowchart of a mode switching method shown according to an embodiment of the invention. DESCRIPTION OF THE EMBODIMENTS Please refer to FIG. 1. A computer system 100 of the present embodiment is, for example, a computer device such as a desktop computer, a notebook computer, or a server. The invention does not limit the type thereof. The computer system 100 includes a processor 110, a memory 120, peripheral components 130_0 to 130_2, and a switch 140. The