US-12625826-B2 - Performance of memory system background operations

Abstract

Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

Inventors

• Kulachet Tanpairoj
• Christian M. Gyllenskog
• David Aaron Palmer

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20240129

Claims (20)

1. 1 . An electronic device, comprising: a memory system comprising a memory controller and a plurality of memory locations, the memory controller being programmed to perform operations comprising: communicating, to a host device, a first message describing at least one background operation to be performed at the memory system; receiving, from the host device, a second message indicating permission to execute the at least one background operation described by the first message to the host device, the second message being responsive to the first message; initiating execution of the at least one background operation; while executing the at least one background operation, receiving an indication from the host device that the memory system is to stop execution of the at least one background operation; and responsive to the indication that that the memory system is to stop execution of the at least one background operation, stopping execution of the at least one background operation.
2. 2 . The electronic device of claim 1 , wherein the first message comprises volume data describing a volume of background operations to be performed at the memory system.
3. 3 . The electronic device of claim 1 , wherein communicating the first message comprises writing background operations data to a memory location of the plurality of memory locations that is accessible to the host device.
4. 4 . The electronic device of claim 1 , wherein the second message indicates a time period when the memory system is to execute the at least one background operation.
5. 5 . The electronic device of claim 1 , the indication that the memory system is to stop execution of the at least one background operation comprising a stop background operation interrupt signal received from the host device.
6. 6 . The electronic device of claim 1 , the indication that the memory system is to stop execution of the at least one background operation comprising an indication that a temperature of the memory system has exceeded a maximum temperature.
7. 7 . The electronic device of claim 1 , the operations further comprising, reading time data from a descriptor memory location, the time data describing a time period when the memory system is to execute the at least one background operation, the descriptor memory location being a memory location of the plurality of memory locations that is accessible to the host device the indication that the memory system is to stop execution of the at least one background operation comprising an indication that the time period when the memory system is to execute the at least one background operation has expired prior to completing the at least one background operation.
8. 8 . The electronic device of claim 1 , the operations further comprising, after completing the at least one background operation, writing background operations stopped data to a descriptor memory location, the background operations stopped data indicating that at least one background operation is complete, the descriptor memory location being a memory location of the plurality of memory locations that is accessible to the host device.
9. 9 . A method for executing background operations at a memory system comprising a plurality of memory locations, the method comprising: communicating, by the memory system and to a host device, a first message describing at least one background operation to be performed at the memory system; receiving, by the memory system and from the host device, a second message indicating permission to execute the at least one background operation described by the first message to the host device, the second message being responsive to the first message; initiating, by the memory system, execution of the at least one background operation; while executing the at least one background operation, receiving, by the memory system, an indication from the host device that the memory system is to stop execution of the at least one background operation; and responsive to the indication that the memory system is to stop execution of the at least one background operation, stopping, by the memory system, execution of the at least one background operation.
10. 10 . The method of claim 9 , wherein the first message comprises volume data describing a volume of background operations to be performed at the memory system.
11. 11 . The method of claim 9 , wherein communicating the first message comprises writing background operations data to a memory location of the plurality of memory locations that is accessible to the host device.
12. 12 . The method of claim 9 , wherein the second message indicates a time period when the memory system is to execute the at least one background operation.
13. 13 . The method of claim 9 , the indication that the memory system is to stop execution of the at least one background operation comprising a stop background operation interrupt signal received from the host device.
14. 14 . The method of claim 9 , the indication that the memory system is to stop execution of the at least one background operation comprising an indication that a temperature of the memory system has exceeded a maximum temperature.
15. 15 . The method of claim 9 , further comprising, reading, by the memory system, time data from a descriptor memory location, the time data describing a time period when the memory system is to execute the at least one background operation, the descriptor memory location being a memory location of the plurality of memory locations that is accessible to the host device the indication that the memory system is to stop execution of the at least one background operation comprising an indication that the time period when the memory system is to execute the at least one background operation has expired prior to completing the at least one background operation.
16. 16 . The method of claim 9 , further comprising, after completing the at least one background operation, writing, by the memory system, background operations stopped data to a descriptor memory location, the background operations stopped data indicating that at least one background operation is complete, the descriptor memory location being a memory location of the plurality of memory locations that is accessible to the host device.
17. 17 . A non-transitory computer-readable medium comprising instructions thereon that, when executed by at least one processor of a memory system, causes the at least one processor to perform operations comprising: communicating, to a host device, a first message describing at least one background operation to be performed at the memory system, the memory system comprising a plurality of memory locations; receiving, from the host device, a second message indicating permission to execute the at least one background operation described by the first message to the host device, the second message being responsive to the first message; initiating execution of the at least one background operation; while executing the at least one background operation, receiving accessing an indication from the host device that the memory system is to stop execution of the at least one background operation; and responsive to the indication that the memory system is to stop execution of the at least one background operation, stopping execution of the at least one background operation.
18. 18 . The non-transitory computer-readable medium of claim 17 , wherein the first message comprises volume data describing a volume of background operations to be performed at the memory system.
19. 19 . The non-transitory computer-readable medium of claim 17 , wherein communicating the first message comprises writing background operations data to a memory location of the plurality of memory locations that is accessible to the host device.
20. 20 . The non-transitory computer-readable medium of claim 17 , wherein the second message indicates a time period when the memory system is to execute the at least one background operation.

Description

PRIORITY This application is a continuation of U.S. application Ser. No. 17/111,195, filed Dec. 3, 2020, which claims the benefit of U.S. Provisional Patent Application Ser. No. 62/955,719 filed on Dec. 31, 2019, all of which are incorporated herein by reference in their entirety. BACKGROUND Memory devices are typically provided as internal semiconductor circuits in that provide electronic storage of data for a computer or other electronic device. Memory devices may be volatile or non-volatile. Volatile memory requires power to maintain data and includes devices such as random-access memory (RAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), or synchronous dynamic random-access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase change random access memory (PCRAM), resistive random-access memory (RRAM), or magnetoresistive random access memory (MRAM), and three-dimensional (3D)-Xpoint memory, among others. Computers and other electronic devices typically include a host device and one or more memory systems. The host device includes a processor and a first amount of main memory (e.g., often volatile memory, such as DRAM) to support the host processor. The one or more memory systems (e.g., often non-volatile memory, such as flash memory) are in communication with the host device to provide additional storage, such as to retain data in addition to or separate from the main memory. A memory system (e.g., a solid-state drive (SSD), a managed memory device (for example, a managed NAND memory device)), can include a memory controller and one or more memory devices, including a number of (e.g., multiple) dies or logical units (LUNs). In certain examples, each die can include a number of memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller can include interface circuitry configured to communicate with a host device (e.g., the host processor or interface circuitry) through a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller can receive commands or operations from the host device in association with memory operations or instructions, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data or address data, etc.) between the memory devices and the host device and erase operations to erase data from the memory devices. The memory controller can also perform memory management operations (e.g., data migration, garbage collection, block retirement). BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. FIG. 1 shows an example electronic device including a host device and a memory system. FIG. 2 shows an example electronic device including a host and a memory system and showing signals between the host and the memory system. FIG. 3 is a flowchart showing one example of a process flow for performing memory system background operations. FIG. 4 is a flowchart showing another example of a process flow for performing memory system background operations. FIG. 5 is a flowchart showing one example of a process flow that may be executed by the host device and the memory system to execute background operations at the memory system. FIG. 6 shows one example of an electronic device including a host device and a memory system, where the memory system includes a Universal Flash Storage (UFS) device. FIG. 7 is a flowchart showing one example of a process flow that may be executed by a memory system to provide a device descriptor, attribute, and/or flag in response to a request. FIG. 8 is a flowchart showing one example of a process flow that may be executed by a host device to read a device descriptor, attribute, and/or flag of a memory device. FIG. 9 is a flowchart showing one example of a process flow that may be executed by a memory system to execute background operations utilizing UFS-compliant communications with a host device. FIG. 10 shows an environment including an example electronic device shown as part of one or more apparatuses. FIG. 11 shows a block diagram of an example machine upon which any one or more of the techniques (e.g., methodologies) discussed herein may perform. DESCRIPTION With a seemingly ever increasing use of host devices and memory devices in electronic devices, which often spend much of their operating time on battery power, performing