US-12625827-B2 - Operating method of an electronic device

Abstract

An operating method of an electronic device which includes a processor and a memory, the method including: accessing, using the processor, the memory without control of an external host device in a first bias mode; sending, from the processor, information of the memory to the external host device when the first bias mode ends; and accessing, using the processor, the memory under control of the external host device in a second bias mode.

Inventors

• Insoon JO

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20241108

Priority Date

20211201

Claims (15)

1. 1 . An electronic device comprising: a first processor; a second processor; a first memory; and a second memory, wherein the first processor is configured to: access the first memory without control of an external host device in a first bias mode; send information of the first memory to the external host device when the first bias mode ends; switch to a second bias mode from the first bias mode by invalidating cache lines including data modified in the first bias mode and, after invalidating the cache lines, in response to the external host requesting modified data, providing the requested data to the external host device using cache miss handling; and access the first memory under control of the external host device in the second bias mode, wherein the second processor is configured to access the second memory under control of the external host device, while the first memory is accessed in the first mode without control of the external host device.
2. 2 . The electronic device of claim 1 , wherein the first processor is further configured to: enter the first bias mode from the second bias mode by: receiving data from the external host device; and updates the first memory with the received data.
3. 3 . The electronic device of claim 2 , wherein the first processor is further configured to enter the first bias mode from the second bias mode by: sending the received data to the external host device; and entered the first bias mode in response to an acknowledgement message received from the external host device.
4. 4 . The electronic device of claim 2 , wherein the received data correspond to at least one cache line.
5. 5 . The electronic device of claim 1 , wherein the first processor is further configured to: access the first memory without control of the external host device in a third bias mode.
6. 6 . The electronic device of claim 5 , wherein the second bias mode is a host bias mode of the Compute Express Link standard, and the third bias mode is a device bias mode of the Compute Express Link standard.
7. 7 . An electronic device comprising: a first processor; a second processor; a first memory; and a second memory, wherein the first processor is configured to: not intervene in an access of an external electronic device to a memory of the external electronic device, in a first bias mode; receive information of the memory of the external electronic device from the external electronic device when the first bias mode ends; switch to a second bias mode from the first bias mode by invalidating cache lines including data modified in the first bias mode and, after invalidating the cache lines, in response to the external electronic device requesting modified data from the first processor, providing the requested data to the external electronic device using cache miss handling; and control the access of the external electronic device to the memory of the external electronic device, in the second bias mode, wherein the second processor is configured to control the access of the external electronic device to the second memory while not intervening, with the first processor, in the access of the external electronic device to the memory of the external electronic device, in the first bias mode.
8. 8 . The electronic device of claim 7 , wherein the first processor is further configured to: enter the first bias mode from the second bias mode by: detecting data modified in association with the external electronic device from among data of the first memory; and sending the modified data to the external electronic device.
9. 9 . The electronic device of claim 8 , wherein the first processor is further configured to enter the first bias mode from the second bias mode by: receiving data from the external electronic device; and sending an acknowledgement message to the external electronic device in response to the modified data and the received data being matched.
10. 10 . The electronic device of claim 7 , wherein the first processor is further configured to: maintain data of a storage space allocated to the first memory in association with the memory of the external electronic device, in the first bias mode.
11. 11 . The electronic device of claim 7 , wherein the first processor is further configured to: receive data corresponding to the information of the memory of the external electronic device from the external electronic device when the first bias mode ends; and replace data of the memory with the received data based on the information of the memory of the external electronic device.
12. 12 . An electronic device comprising: a host device; and an accelerator, wherein, the host device is configured to: maintain a coherency of a memory of the accelerator and a memory of the host device while the accelerator does not perform an operation; block the coherency of the memory of the accelerator and the memory of the host device while the accelerator performs an operation; recover the coherency of the memory of the accelerator and the memory of the host device after the accelerator completes the operation by invalidating cache lines including modified data of data included in the memory of the accelerator and providing the modified data to the host device using cache miss handling; and maintain the coherency of another memory of another accelerator while the coherency of the memory of the accelerator and the memory of the host device is blocked while the accelerator performs the operation.
13. 13 . The electronic device of claim 12 , wherein the host device is further configured to block the coherency of the memory of the accelerator and the memory of the host device by: sending the modified data to the accelerator; and replacing the data of the memory of the accelerator with the modified data.
14. 14 . The electronic device of claim 12 , wherein the accelerator is further configured to send information of the cache lines of the modified data to the host device, and wherein the host device if further configured to: invalidate data corresponding to the information of the cache lines of the modified data in the memory of the host device; and in response to a request for the modified data, read the modified data from the accelerator to update the data of the memory of the host device.
15. 15 . The electronic device of claim 12 , wherein the accelerator is further configured to: send information of the cache lines of the modified data to the host device; and send the modified data to the host device, wherein the host device if further configured to replace data of the memory of the host device with the modified data based on the information of the cache lines of the modified data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 17/867,754 filed on Jul. 19, 2022, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0170435 filed on Dec. 1, 2021, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. TECHNICAL FIELD Embodiments of the present disclosure relate to an electronic device, and more particularly, to an electronic device supporting an independent operation together with providing a cache coherency. DISCUSSION OF RELATED ART Cache coherency is the uniformity of shared resource data that ends up stored in multiple local caches. Cache coherency is a concern when a first electronic device and a second electronic device share specific data. For example, when the first electronic device and the second electronic device support the cache coherency, specific data stored in the second electronic device are also modified when the first electronic device modifies the specific data. The cache coherency may be required when a plurality of processors (or processor cores) process data in a state where the data are shared by the processors. Since electronic devices using multiple cores are widely used, research on how to support the cache coherency continues. SUMMARY Embodiments of the present disclosure provide an operating method of an electronic device capable of partially blocking cache coherency such that an independent operation is possible, together with supporting the cache coherency. According to an embodiment of the present disclosure, there is provided an operating method of an electronic device which includes a processor and a memory, the method including: accessing, using the processor, the memory without control of an external host device in a first bias mode; sending, from the processor, information of the memory to the external host device when the first bias mode ends; and accessing, using the processor, the memory under control of the external host device in a second bias mode. According to an embodiment of the present disclosure, there is provided an operating method of an electronic device which includes a processor and a memory, the method including: not intervening, with the processor, in an access of an external electronic device to a memory of the external electronic device, in a first bias mode; receiving, at the processor, information of the memory of the external electronic device from the external electronic device when the first bias mode ends; and controlling, using the processor, the access of the external electronic device to the memory of the external electronic device, in a second bias mode. According to an embodiment of the present disclosure, there is provided an operating method of an electronic device which includes a host device and an accelerator, the method including: maintaining, using the host device, a coherency of a memory of the accelerator and a memory of the host device while the accelerator does not perform an operation; blocking, using the host device, the coherency of the memory of the accelerator and the memory of the host device while the accelerator performs an operation; and recovering, using the host device, the coherency of the memory of the accelerator and the memory of the host device after the accelerator completes the operation. BRIEF DESCRIPTION OF THE FIGURES The above and other features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings. FIG. 1 illustrates an electronic device according to an embodiment of the present disclosure. FIG. 2 illustrates an example of an operating method of an electronic device according to an embodiment of the present disclosure. FIG. 3 illustrates an example of a process in which a coherency host and a first coherency device enter a first bias mode from a second bias mode according to an embodiment of the present disclosure. FIG. 4 illustrates an example of a process in which a coherency host and a first coherency device enter a second bias mode from a first bias mode according to an embodiment of the present disclosure. FIG. 5 illustrates another example of a process in which a coherency host and a first coherency device enter a second bias mode from a first bias mode according to an embodiment of the present disclosure. FIG. 6 illustrates an example corresponding to the case where an electronic device is in a second bias mode before entering a first bias mode according to an embodiment of the present disclosure. FIG. 7 illustrates an example corresponding to the case where an electronic device operates in a first bias mode according to an embodiment of the present disclosure. FIG. 8 illustrates an example corresponding to the case where an electronic device completes processing in a first bias mode and enters a second bias mode according to an embodim