Search

US-12625828-B2 - NVMe completion and interrupt

US12625828B2US 12625828 B2US12625828 B2US 12625828B2US-12625828-B2

Abstract

Instead of having uncertainty when waiting on completions, utilize unordered input output memory write (UIOMWr) to ensure the completions of the write. Using UIOMWr, the data storage device will write the competitions to a host dynamic random access memory (DRAM). When the device receives an approval of the completion, the device knows that the write to the host DRAM was successful. The approval will trigger the device to have the message signaled interrupts extended (MSIx) send an interrupt request (IRQ) to the host. The IRQ will pass through the PCIe and will be received by the host CPU. The host CPU will then process any pending completions in the host DRAM. An MSIx tag can be added to the completion (at the UIOMWr TLP level) that is assigned to multiple submission queues (SQ). When the MSIx tag is received by the host and device, the host and device will know what information needs to be pulled to avoid the need for translation later on.

Inventors

  • Amir Segev
  • Shay Benisty

Assignees

  • SanDisk Technologies, Inc.

Dates

Publication Date
20260512
Application Date
20231129

Claims (17)

  1. 1 . A data storage device, comprising: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: send a nonvolatile memory express (NVMe) completion to a host device, wherein the NVMe completion has a tag, the tag being assigned to two or more completion queues of the host device; send multiple NVMe completions to a same completion queue of the two or more completion queues utilizing multiple transaction layer packets (TLPs), wherein other TLPs of the multiple TLPs excluding a last TLP of the multiple TLPs do not use unordered input output memory write (UIOMWr); receive a peripheral component interconnect express (PCle) completion from the host device, wherein the PCle completion has the tag; and send an interrupt to the host device.
  2. 2 . The data storage device of claim 1 , wherein the tag is an indication of which message signaled interrupts extended (MSIx) or message signaled interrupt (MSI) or interrupt extended (INTx) to utilize.
  3. 3 . The data storage device of claim 1 , wherein the NVMe completion is for a first completion queue of the two or more completion queues and the PCle completion is for the first completion queue.
  4. 4 . The data storage device of claim 1 , wherein the controller uses UIOMWr to write the NVMe completion.
  5. 5 . The data storage device of claim 4 , wherein the controller is configured to send multiple UIOMWr completions with the same tag as the NVMe completion tag.
  6. 6 . The data storage device of claim 1 , wherein the controller is configured to increase a counter when sending the NVMe completion.
  7. 7 . The data storage device of claim 6 , wherein the controller is configured to decrease the counter when receiving the PCle completion.
  8. 8 . The data storage device of claim 7 , wherein the sending an interrupt is performed when the counter reaches 0 after being decreased to 0.
  9. 9 . The data storage device of claim 1 , wherein the interrupt is sent after multiple PCle completions have been received for a same completion queue.
  10. 10 . The data storage device of claim 1 , wherein the last TLP of the multiple TLPs uses UIOMWr.
  11. 11 . A data storage device, comprising: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: send a first device completion notification to a completion queue of a host device; send a second device completion notification to the completion queue of the host device, wherein the second device completion notification is sent prior to receiving a first host completion notification from the host device for the first device completion notification; maintain a counter for completion notifications, wherein the counter is increased when sending each device completion notification, and wherein the counter is decreased when receiving each host completion notification; and send an interrupt to the host device, wherein the interrupt is sent after receiving a second host completion notification from the host device for the second device completion notification, wherein the interrupt is sent when the counter is 0 after being decreased to 0.
  12. 12 . The data storage device of claim 11 , wherein the interrupt is an message signaled interrupts extended (MSIx) interrupt, a message signaled interrupt (MSI) interrupt, or an interrupt extended (INTx) interrupt.
  13. 13 . A data storage device, comprising: means to store data; and a controller coupled to the means to store data, wherein the controller is configured to: send multiple transaction layer packets (TLPs) to a completion queue of a host device, the completion queue being assigned to a tag, wherein a last TLP of the multiple TLPs includes a uses unordered input output memory write (UIOMWr), and wherein other TLPs of the multiple TLPs excluding the last TLP do not include UIOMWr; and send an interrupt to the host device after receiving an acknowledgement of the last TLP based on the last TLP having the UIOMWr.
  14. 14 . The data storage device of claim 13 , wherein interrupts are not sent to the host device after the other TLPs.
  15. 15 . The data storage device of claim 13 , wherein the controller is configured to send multiple UIOMWr completions with different tags.
  16. 16 . The data storage device of claim 13 , wherein the controller is configured to increase a counter when completions are sent, and decrease the counter when the controller determines that a host completion response has been received, and wherein a counter and a tag are different based on an message signaled interrupts extended (MSIx) vectors.
  17. 17 . The data storage device of claim 13 , wherein the controller is further configured to create a plurality of completion queues (CQs).

Description

BACKGROUND OF THE DISCLOSURE Field of the Disclosure Embodiments of the present disclosure generally relate to improving completion recognition in solid state drives (SSD). Description of the Related Art SSD non-volatile memory express (NVMe) devices, use a completion queue to report a success or a failure of command. Once the completion information is written in the completion queue, the host receives an interrupt via the message signaled interrupts extended (MSIx) to inform the host, that the host has completions to manage. Usually with the presence of completions and interrupts, the data storage device would send the completion to the host. Once the completion is sent, the data storage device would then send the interrupt to the MSIx. Once the host receives the interrupt, the host will go and decide whether to read the completion entry or not. The peripheral component interconnect express (PCIe) guarantees the order of completion. Writing the completion will be finished first before writing the interrupt, the finishing ends at the PCIe controller ensuring that there are no bypass at the PCIe level. A completion typically goes to a dynamic random access memory (DRAM), and MSIx typically goes to the PCIe. If the CPU doesn't receive the interrupt, then the CPU will check again for the interrupt at a predetermined time. After sending the completion, sometime later the host is expected to say the completion was received so the data storage device knows the host did receive the completion. If a completion is not notified to the data storage device, then the data storage device will resend the interrupt as a check. The host could back-pressure any MSIx (and following memory write (MemWr)) until the PCIe to DRAM path is empty, but that will cause performance degradation. Alternatively, the data storage device could hold a time-out mechanism and if the data storage device sees the completions have not been approved, the data storage device will re-issue the MSIx, but such a procedure is not efficient. Therefore, there is a need in the art for improving completion notifications between the host and the data storage device. SUMMARY OF THE DISCLOSURE Instead of having uncertainty when waiting on completions, utilize unordered input output memory write (UIOMWr) to ensure the completions of the write. Using UIOMWr, the data storage device will write the competitions to a host dynamic random access memory (DRAM). When the device receives an approval of the completion, the device knows that the write to the host DRAM was successful. The approval will trigger the device to have the message signaled interrupts extended (MSIx) send an interrupt request (IRQ) to the host. The IRQ will pass through the PCIe and will be received by the host CPU. The host CPU will then process any pending completions in the host DRAM. An MSIx tag can be added to the completion (at the UIOMWr TLP level) that is assigned to multiple submission queues (SQ). When the MSIx tag is received by the host and device, the host and device will know what information needs to be pulled to avoid the need for translation later on. In one embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: send a nonvolatile memory express (NVMe) completion to a host device, wherein the NVMe completion has a tag; receive a peripheral component interconnect express (PCIe) completion from the host device, wherein the PCIe completion has the tag; and send an interrupt to the host device. In another embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: send a first device completion notification to a completion queue of a host device; send a second device completion notification to the completion queue of the host device, wherein the second device completion notification is sent prior to receiving a first host completion notification from the host device for the first device completion notification; and send an interrupt to the host device, wherein the interrupt is sent after receiving a second host completion notification from the host device for the second device completion notification. In another embodiment, a data storage device comprises: means to store data; and a controller coupled to the means to store data, wherein the controller is configured to: send multiple transaction layer packets (TLPs) to a completion queue of a host device, wherein a last TLP includes a uses unordered input output memory write (UIOMWr); and send an interrupt to the host device after receiving an acknowledgement of the last TLP. BRIEF DESCRIPTION OF THE DRAWINGS So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illus