US-12625830-B2 - Semiconductor device

US12625830B2US 12625830 B2US12625830 B2US 12625830B2US-12625830-B2

Abstract

An interrupt reception unit receives an interrupt request. In response to a received interrupt request, an interrupt processing unit performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.

Inventors

Susumu Hirata

Assignees

RENESAS ELECTRONICS CORPORATION

Dates

Publication Date: 20260512
Application Date: 20241029
Priority Date: 20231215

Claims (12)

1 . A semiconductor device circuit comprising: a main processing unit that is configured to start up a main process every start of a cycle time; a plurality of communication interfaces that is coupled to a communication bus and is configured to output an interrupt request; an interrupt reception unit that is configured to receive the interrupt request; an interrupt processing unit that is configured to perform an interrupt process including an interrupt process of a first priority and an interrupt process of a second priority having a lower priority than the first priority, the interrupt processing unit being configured to perform, in response to the interrupt request received by the interrupt reception unit, the interrupt process of the first priority or the interrupt process of the second priority; and an interrupt suppression control unit that is configured to control a number of the interrupt processes of the second priority processed by the interrupt processing unit in the cycle time, according to a first suppression condition set on a basis of a cycle in which the interrupt process of the second priority occurs and a total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.
2 . The semiconductor device circuit according to claim 1 , wherein the first suppression condition defines an upper limit of a number of times of the interrupt process of the second priority performed by the interrupt processing unit in the cycle time, and wherein the interrupt suppression control unit is configured to perform control of the interrupt suppression by using an interrupt suppression table including the suppression condition.
3 . The semiconductor device circuit according to claim 2 , wherein the interrupt suppression table includes an interrupt suppression target that defines a communication interface corresponding to the interrupt process of the second priority among the plurality of communication interfaces, and wherein the interrupt suppression control unit includes: a suppression target determination unit that is configured to determine whether or not an interrupt request received by the interrupt reception unit is an interrupt request output from the communication interface registered as the interrupt suppression target; a counter that is configured to count a number that the received interrupt request is determined as an interrupt request output from the communication interface registered as the interrupt suppression target; and a suppression determination unit that is configured to determine whether or not to suppress the interrupt request output from the communication interface registered as the interrupt suppression target, on a basis of a count value of the counter and the upper limit of the number of times defined by the first suppression condition.
4 . The semiconductor device circuit according to claim 3 , wherein the suppression determination unit is configured to determine to suppress the interrupt request output from a communication interface registered as the interrupt suppression target in a case where a count value of the counter reaches the upper limit of the number of times defined by the first suppression condition.
5 . The semiconductor device circuit according to claim 3 , wherein the suppression determination unit is configured to suppress the interrupt request output from a communication interface registered as the interrupt suppression target by outputting a suppression signal configured to suppress output of the interrupt request to the communication interface registered as the interrupt suppression target.
6 . The semiconductor device circuit according to claim 5 , wherein the suppression determination unit is configured to release the output of the suppression signal every time the cycle time starts.
7 . The semiconductor device circuit according to claim 3 , wherein the interrupt suppression control unit further includes an initialization unit that is configured to initialize the counter every time the cycle time starts.
8 . The semiconductor device circuit according to claim 1 , wherein the interrupt process of the second priority occurs at a cycle indicated by N times the cycle time, where N is a natural number.
9 . The semiconductor device circuit according to claim 8 , wherein the interrupt suppression control unit is configured to use m as a natural number indicating a total number of the interrupt processes of the second priority occurring in a period corresponding to the cycle to control a number of the interrupt processes of the second priority processed by the interrupt processing unit within one of the cycle times to be equal to or less than an integer obtained by rounding up a decimal of a value of m/N.
10 . The semiconductor device circuit according to claim 1 , further comprising a suppression condition setting unit that is configured to use, as inputs, a value of a natural number N indicating a cycle in which the interrupt process of the second priority occurs and a value of a natural number m indicating a total number of the interrupt processes of the second priority occurring in a period corresponding to the cycle to calculate an integer obtained by rounding up a decimal of a value of m/N, and to set the calculated integer as the first suppression condition.
11 . The semiconductor device circuit according to claim 1 , wherein the interrupt process includes an interrupt process of a third priority having a priority lower than the second priority, wherein the interrupt processing unit is configured to perform the interrupt process of the first priority, the interrupt process of the second priority, or the interrupt process of the third priority in response to an interrupt request received by the interrupt reception unit, and wherein the interrupt suppression control unit is configured to further control a number of the interrupt processes of the third priority to be processed by the interrupt processing unit in the cycle time according to a second suppression condition set on a basis of a cycle in which the interrupt process of the third priority occurs and a total number of the interrupt processes of the third priority occurring within a period corresponding to the cycle.
12 . The semiconductor device circuit according to claim 11 , wherein the interrupt process of the second priority occurs at a cycle indicated by N1 times the cycle time, where N1 is a natural number, and the interrupt process of the third priority occurs at a cycle indicated by N2 times the cycle time, where N2 is a natural number, and wherein the interrupt suppression control unit is configured to use m1 as a natural number indicating a total number of the interrupt processes of the second priority occurring in a period of N1 times the cycle time to control a number of the interrupt processes of the second priority processed by the interrupt processing unit within one of the cycle times to be equal to or less than an integer obtained by rounding up a decimal of a value of m1/N1, and to use m2 as a natural number indicating a total number of the interrupt processes of the third priority occurring in a period of N2 times the cycle time to control a number of the interrupt processes of the third priority processed by the interrupt processing unit within one of the cycle times to be equal to or less than an integer obtained by rounding up a decimal of a value of m2/N2.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The disclosure of Japanese Patent Application No. 2023-212030 filed on Dec. 15, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. BACKGROUND This disclosure relates to a semiconductor device, and for example, relates to a semiconductor device having a processor that performs an interrupt process. There are disclosed techniques listed below. [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2010-086456 As a related art, Patent Document 1 discloses a data processing system excellent in immediacy of the interrupt process. The data processing system described in Patent Document 1 includes a plurality of central processing units, a plurality of interrupt controllers separately allocated to the central processing units, and a circuit module that can be commonly used by the plurality of central processing units. The plurality of interrupt controllers are supplied with separate interrupt request signals from the circuit module. The plurality of interrupt controllers each notify the corresponding central processing unit of the interrupt in response to the input interrupt request signal. SUMMARY In recent years, since an in-vehicle micro controller unit (MCU) or system on a chip (SoC) exchanges information with a large number of electronic control units (ECUs), the number of asynchronous communications has been increasing. In the in-vehicle MCU, the amount of the interrupt process of the asynchronous communication system is increasing by the number of increase in the asynchronous communication. A processor such as a central processing unit (CPU) mounted on the in-vehicle MCU performs application processes and processes of asynchronous communication information. In the CPU, as the amount of the asynchronous interrupt processes increases, the time allocated to the application process becomes short. In view of such a problem, there is a demand for a mechanism that can secure the time allocated to the application process even in a case where the asynchronous communication increases. Other problems and novel features will become apparent from the description of the present specification and the accompanying drawings. According to an embodiment, a semiconductor device is provided. In the semiconductor device, in response to an interrupt request, an interrupt processing unit performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle. According to the embodiment, the time that can be allocated to a main process can be increased. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to a first embodiment of this disclosure. FIG. 2 is a diagram illustrating an example of an interrupt suppression table corresponding to a certain CPU core. FIG. 3 is a block diagram illustrating an example of a logical configuration of a CPU. FIG. 4 is a block diagram illustrating a configuration example of a communication interface. FIG. 5 is a flowchart illustrating an operation procedure of an MCU at the time when a timer interrupt occurs. FIG. 6 is a flowchart illustrating an operation procedure of the MCU in a case where an interrupt request is output from the communication interface. FIG. 7 is a schematic diagram schematically illustrating execution of processes performed by the CPU. FIG. 8 is a block diagram illustrating a configuration example of a semiconductor device according to a second embodiment of this disclosure. FIG. 9 is a diagram illustrating an example of an interrupt suppression table used in a third embodiment. DETAILED DESCRIPTION Prior to the description of embodiments, the background leading to the following embodiments will be described. In an MCU such as an in-vehicle MCU, a CPU performs an interrupt process occurring from a plurality of asynchronous communications while executing a predetermined application process (hereinafter, also referred to as a main process). The main process includes, for example, a high-priority main process and the main process other than the high-priority main process. As the high-priority main process, there is a process of a chassis system that controls turning and stopping of a vehicle. In addition, as the main process of other than high priority, there are a process of a power train system and a process of a body system. The main process is started up every start of a pre