US-12625833-B2 - Flexible power management interface

Abstract

Systems and methods are described for a flexible and selectable power management interface. The flexible and selectable power management interface can provide multiple power management interfaces which are selectable based on a selected processor IP core, a selected power management controller, and a variety of factors. The flexible and selectable power management interface can be a direct handshake hardware interface, a memory-mapped bus interface, or a combination of the direct handshake hardware interface and the memory-mapped bus interface.

Inventors

• Edward McLellan
• Arjun Pal Chowdury

Assignees

• SiFive, Inc.

Dates

Publication Date

20260512

Application Date

20231009

Claims (20)

1. 1 . One or more non-transitory computer-readable storage media storing instructions that, upon execution by processing circuitry, cause operations comprising: providing multiple power management interfaces for communication between a processor core and a power management controller, wherein a power management interface of the multiple power management interfaces has a type and is selected, based on a set of factors, from one of: a direct handshake hardware interface; a memory-mapped bus interface; and a combination of the direct handshake hardware interface and the memory-mapped bus interface, wherein the set of factors relates to an architecture of the processor core, and wherein the processor core implements an interface to the power management controller independently of the type of the power management interface.
2. 2 . The one or more non-transitory computer-readable storage media of claim 1 , wherein each one of the multiple power management interfaces is selected from one of the direct handshake hardware interface, the memory-mapped bus interface, or the combination of the direct handshake hardware interface and the memory-mapped bus interface.
3. 3 . The one or more non-transitory computer-readable storage media of claim 2 , wherein registers are allocated based on the power management interface being the memory-mapped bus interface.
4. 4 . The one or more non-transitory computer-readable storage media of claim 3 , wherein a first register is allocated in a power domain and a second register is allocated external to the power domain for use by the power management controller.
5. 5 . The one or more non-transitory computer-readable storage media of claim 3 , wherein the communication between an internal controller of the processor core and the power management controller is based on a protocol that supports both the direct handshake hardware interface and the memory-mapped bus interface.
6. 6 . The one or more non-transitory computer-readable storage media of claim 5 , wherein the protocol is used by the internal controller or the power management controller to initiate at least one of an idle power mode transition or an active mode transition at a power domain.
7. 7 . The one or more non-transitory computer-readable storage media of claim 5 , wherein the power management controller is selected based on a power domain.
8. 8 . A method comprising: providing multiple power management interfaces for communication between a processor core and a power management controller, wherein a power management interface of the multiple power management interfaces has a type and is selected, based on a set of factors, from one of: a direct handshake hardware interface; a memory-mapped bus interface; and a combination of the direct handshake hardware interface and the memory-mapped bus interface, wherein the set of factors relates to an architecture of the processor core, and wherein the processor core implements an interface to the power management controller independently of the type of the power management interface.
9. 9 . The method of claim 8 , wherein the power management controller is external to the processor core, the processor core includes an internal controller, and the power management interface communicates between the power management controller and the internal controller.
10. 10 . The method of claim 9 , further comprising: providing registers when the memory-mapped bus interface is selected for communication between the internal controller and the power management controller.
11. 11 . The method of claim 10 , wherein some of the registers are allocated in the processor core and some of the registers are allocated external to the processor core for use by the power management controller.
12. 12 . The method of claim 10 , further comprising: providing a protocol for communication between the internal controller and the power management controller which can work with both the direct handshake hardware interface and the memory-mapped bus interface.
13. 13 . The method of claim 12 , wherein the protocol is used by the internal controller or the power management controller to initiate at least one of an idle power mode transition or an active power mode transition at the processor core.
14. 14 . A processing system comprising: at least one power domain; a power management controller; and a power management interface for communication between the at least one power domain and the power management controller, wherein the power management interface has a type that is selected, based on a set of factors, from one of: a direct handshake hardware interface; a memory-mapped bus interface; and p 2 a combination of the direct handshake hardware interface and the memory-mapped bus interface, wherein the set of factors includes at least one of: a number of power domains, a power domain type, a power domain size, a power management mode, a level of power management control, a level of operational control, a level of performance control, or a power level, and wherein the at least one power domain implements an interface to the power management controller independently of the type of the power management interface.
15. 15 . The processing system of claim 14 , wherein the power management controller is external to the at least one power domain, the at least one power domain includes an internal controller, and the power management interface communicates between the power management controller and the internal controller.
16. 16 . The processing system of claim 15 , further comprising: registers configured to enable communications between the internal controller and the power management controller when the power management interface is a memory-mapped bus interface.
17. 17 . The processing system of claim 16 , wherein some of the registers are allocated in the at least one power domain and some of the registers are allocated external to the at least one power domain for use by the power management controller.
18. 18 . The processing system of claim 17 , further comprising: a protocol for communication between the internal controller and the power management controller which is configured to work with both the direct handshake hardware interface and the memory-mapped bus interface.
19. 19 . The processing system of claim 18 , wherein the protocol is used by the internal controller or the power management controller to initiate at least one of an idle power mode transition or an active power mode transition at a processor core.
20. 20 . The processing system of claim 18 , wherein the at least one power domain and the power management controller are selectable.

Description

CROSS REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of U.S. Patent Application Ser. No. 63/429,843, filed on Dec. 2, 2022, the entire disclosure of which is hereby incorporated by reference. TECHNICAL FIELD This disclosure relates generally to integrated circuits and, more specifically, to flexible and selective power management interface architectures. BACKGROUND Power is tied to overall system-on-chip (SoC) performance including, but not limited to, battery life, energy consumption, thermal profile, cooling requirements, noise profile, system stability, sustainability, and operational costs. Power management techniques can be used to control power consumption by controlling the clock rate and by using voltage scaling, power gating, and other techniques. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to-scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. FIG. 1 is a block diagram of an example of a system for facilitating generation and manufacture of integrated circuits. FIG. 2 is a block diagram of an example of a system for facilitating generation of a circuit representation. FIG. 3 is a block diagram of an example of a system including a flexible or selectable power management interface. FIG. 3A is a block diagram of example selectable IP cores and example power management IP cores. FIG. 3B is a flow diagram of an example of an idle power mode transition protocol. FIG. 4 is a block diagram of an example of a system including a flexible or selectable power management interface which is a power management bus. FIG. 5 is a block diagram of an example of a system including a flexible or selectable power management interface which is a direct hardware or wire connection. FIG. 6 is a block diagram of an example of a method for selecting a power management interface in an integrated circuit. FIG. 7 is a diagram of an example display region generated for presenting a web interface to facilitate customized design of an integrated circuit with a selected power management interface. DETAILED DESCRIPTION Power management is a critical aspect of integrated circuits. Performance limitations due to power have resulted in many power management techniques or modes used in chip designs. Increased granularity and specificity of these power modes enable designs to minimize power required to deliver desired performance levels. Power modes often involve modifying operational parameters including dynamic voltage and frequency scaling (DVFS) when circuits are active and dynamically gating or disconnecting portions of the circuit from the power distribution system when circuits are idle. Operational parameter modification is typically done outside of the normal functional operation of the circuit using a power management interface to dedicated power and clock control logic. Disclosed herein are systems and methods for a flexible and selectable power management interface. Processor intellectual property (IP) cores are available in a range of configurations or architectures where the number of cores, clusters, or both can vary. A one size fits all power management interface is not practical or efficient in terms of chip space, costs, and other factors. The flexible and selectable power management interface can provide multiple power management interfaces which are selectable based on a selected processor IP core and a variety of factors. Upon selection of the processor IP core and the power management interface, a system for automated integrated circuit design, such as described in U.S. Pat. No. 11,048,838, filed Aug. 1, 2019, the contents of which are herein incorporated by reference in its entirety, and which is assigned to the Applicant (the “'838 Patent”) and which is included as Appendix A, can be used to generate the integrated circuit, processing system, or SoC. The power management interface can be implemented using a variety of techniques. One implementation can be a direct handshake hardware interface from each power domain under control. In this sense, a power domain can include a core, a tile, a cluster of cores and/or tiles, a complex, and other circuits in a SoC. The direct handshake hardware interface can be suitable for relatively smaller designs with clearly defined requirements and relatively few power domains and modes. Larger designs, with more power domains and modes benefit from a more flexible implementation, such as a shared bus or a memory-mapped bus for better scalability and extensibility. Other implementations can provide a mixed direct handshake hardware interface and a bus interface for different power domains in a SoC Internal control logic in a power domain can be configured to use the di