US-12625834-B2 - Analog circuit

US12625834B2US 12625834 B2US12625834 B2US 12625834B2US-12625834-B2

Abstract

There is provided an analog circuit comprising: a plurality of analog functions, which are divided into at least two groups of analog functions, and an interconnection structure configured to interconnect the plurality of analog functions so as to enable transfer of both voltage and current signals between analog functions among the plurality of analog functions. The interconnection structure comprises at least two hierarchy levels of interconnections, wherein a local-bus hierarchy level is configured to interconnect analog functions of a respective group, and a global-bus hierarchy level is configured to interconnect analog functions of the plurality of groups. The local-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals, and the global-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals.

Inventors

Lars HEIMANN
Bernd ULMANN
Sven KÖPPEL

Assignees

ANABRID GMBH

Dates

Publication Date: 20260512
Application Date: 20210611

Claims (13)

1 . An analog circuit comprising: a plurality of analog functions, which are divided into at least two groups of analog functions; and an interconnection structure configured to interconnect the plurality of analog functions so as to enable transfer of both voltage and current signals between analog functions among the plurality of analog functions, wherein the interconnection structure comprises at least two hierarchy levels of interconnections, wherein a local-bus hierarchy level is configured to interconnect analog functions of a respective group, and a global-bus hierarchy level is configured to interconnect analog functions of the plurality of groups, the local-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals, and the global-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals, wherein the local-bus hierarchy level comprises, for at least one group, at least a first local bus, which is configured to interconnect a set of analog functions of the respective group, and a second local bus, which is configured to interconnect another set of analog functions of the respective group, wherein the first local bus comprises voltage signal lines for transferring voltage signals, the second local bus comprises current signal lines for transferring current signals, and the interconnection structure comprises at least a further hierarchy level of interconnections, wherein at least one intermediate-bus hierarchy level is configured to interconnect analog functions of a set of groups among the plurality of groups, and the at least one intermediate-bus hierarchy level comprises voltage signal lines for transferring voltage signals and/or current signal lines for transferring current signals.
2 . The analog circuit according to claim 1 , wherein the local-bus hierarchy level comprises at least one local bus for each group, which is configured to interconnect analog functions of the respective group, and the global-bus hierarchy level comprises at least one global bus, which is configured to interconnect analog functions of the plurality of groups.
3 . The analog circuit according to claim 2 , wherein the at least one local bus for each group comprises voltage signal lines for transferring voltage signals, and the at least one global bus comprises current signal lines for transferring current signals.
4 . The analog circuit according to claim 3 , wherein the at least one local bus for at least one group further comprises current signal lines for transferring current signals, and/or the at least one global bus further comprises voltage signal lines for transferring voltage signals.
5 . The analog circuit according to claim 4 , wherein any analog function is connected to the local bus for its group and/or the at least one global bus.
6 . The analog circuit according to claim 5 , wherein a current input or output of an analog function is connected to a current signal line, and/or a voltage input or output of an analog function is connected to a voltage signal line, and/or a first analog function in a group, which is connected to a voltage signal line, and a second analog function in the group, which is connected to a current signal line, are interconnected via a voltage-current converter or a current-voltage converter as a third analog function in the group.
7 . The analog circuit according to claim 1 , wherein at least one group comprises voltage-current converters as analog functions, which are configured to extend a fan-in property of an analog function in that current outputs of at least two voltage-current converters, the voltage inputs of which are connected to different voltage signal lines, are connected to a current signal line which is connected with a current input of the analog function, and/or extend a fan-out property of an analog function in that a voltage output of the analog function is connected to a voltage signal line which is connected to voltage inputs of at least two voltage-current converters, the current outputs of which are connected to different current signal lines.
8 . The analog circuit according to claim 1 , wherein at least one group comprises one or more voltage-current converters as analog functions, which are configured to extend a signal bandwidth and/or reduce influence of parasitic resistance in signal transfer in that one or more voltage signals are converted into one or more current signals and the one or more current signals are transferred via at least one global bus between analog functions of different groups.
9 . The analog circuit according to claim 1 , wherein at least one group comprises a voltage-current converter as analog functions, which is configured to compensate gain and/or offset errors of an analog function in that one or more potentiometers of the voltage-current converter are adjusted to calibrate an output signal of the analog function, and/or compensate parasitic resistance at a voltage input of an analog function in that a calibrated current signal and the calibrated current signal with reversed sign are transferred to current inputs of the analog function and an output signal of the analog function is adjusted to zero.
10 . The analog circuit according to claim 1 , wherein a respective set of groups comprises a number of groups, which are located adjacent or close to each other, and/or the at least one intermediate-bus hierarchy level comprises at least one intermediate bus for a set of groups, which is configured to interconnect analog functions of the respective set of groups.
11 . The analog functions according to claim 10 , wherein the at least one intermediate-bus hierarchy level comprises at least a first intermediate bus for a first set of groups; and a second intermediate bus for a second set of groups, wherein the first set of groups comprises a smaller number of groups and/or groups which are located more adjacent or closer to each other as compared with the second set of groups, and the first intermediate bus comprises voltage signal lines for transferring voltage signals, and the second intermediate bus comprises current signal lines for transferring current signals.
12 . The analog circuit according to claim 1 , wherein the analog functions are divided into groups such that a number of links between analog functions in a group is optimized, wherein the plurality of analog functions constitutes a mathematical problem to be solved by the analog circuit, and/or any one of the analog functions is or comprises any one of an integrator, an adder, a multiplier, a voltage-current converter, a comparator, an exponential function, a logarithmic function, a configurable arbitrary function generator or a current-voltage converter and/or any one of the analog functions comprises a functional component configured to realize a respective function, without comprising fan-in and/or fan-out circuitry.
13 . The analog circuit according to claim 1 , wherein the analog circuit is or is comprised in or is dedicated for any one of an analog computer, an analog arithmetic circuit, an analog filter or an analog signal conditioning system, or is comprised in or is dedicated for any one of a hybrid computer, a hybrid arithmetic circuit, a hybrid filter or a hybrid signal conditioning system, and/or the analog circuit is implemented as any one of an integrated circuit, such as-a system-on-chip integration, a microchip or a microprocessor, or a discrete circuit.

Description

FIELD The present disclosure relates to an analog circuit. More specifically, the present disclosure relates to (the design and the operation of) an analog circuit comprising a plurality of analog functions, particularly the interconnection of the plurality of analog functions. BACKGROUND Basically, the present disclosure relates to the interconnection of a plurality of analog functions of an analog circuit or, stated in other words, the signal transfer (or routing) between a plurality of analog functions of an analog circuit. In this regard, an analog circuit may refer to an analog or hybrid computer, an analog or hybrid arithmetic circuit, an analog or hybrid filter, an analog or hybrid signal conditioning system, or the like. As discrete analog computers, integrated analog computers and digital Field Programmable Gate Arrays (FPGAs) are subject to similar challenges in terms of interconnection of or signal transfer (or routing) between components, an overview of conventional techniques for such circuits is given below. In classic analog computers, the individual computing elements, such as integrators, multipliers, adders and other functions, are connected via a so-called patch panel. The patch panel is a matrix of sockets to which the inputs and outputs of the individual computing elements are connected, wherein the computing elements are interconnected via patch cables. The advantage of patch panels is that any element can be connected with any other element, and there is no restriction by a limited number of signal lines. The disadvantage of patch panels is that the interconnection has to be done manually, and for each new program, i.e. each mathematical problem to be solved by the analog computer, the interconnection has to be manually changed. Even with an exchangeable patch panel, where the program (in form of the interconnection of element) could thus be exchanged, the disadvantage of the need of manual implementation of the program remained. Therefore, the patch panel was replaced with an electronic switching matrix. However, in such switching matrix, the extremely high number of switches is problematic. For example, if there are 100 arithmetic elements, a switching matrix of at least 100×100=10,000 switches is needed. Since a computing element typically has more than one input and one output, much more switches are typically required in practice. In addition to the high number of switches, parasitic capacitances in the signal lines and the switches themselves also represent disadvantages of such switching matrix. The number of switches can be reduced by designing the switching matrix with multiple stages. Such switching networks are called Clos networks, which were used early in communications engineering. The multistage Clos networks have fewer switches overall and can be designed so that each input node can always be connected to each output node. Network (i.e. circuit) overhead can be reduced, if it is possible to reconfigure the entire network when another connection is required. This is the case with analog computers because a new connection is equivalent to a new program, i.e. a new configuration. The effort can be reduced even further, if a small number of desired connections do not have to be implemented. While this is acceptable in telephone networks, it is not acceptable in analog computers. Further, a Clos network has at least three stages, which is why there are at least three switches in series, which further reduces the signal bandwidth due to parasitic capacitances and, if transistors are used as switches, the bandwidth from a combination of capacitances and on-resistances of switches. In Field Programmable Gate Arrays (FPGA), the interconnection of or signal transfer (or routing) between components, which are called Configurable Logic Blocks (CLBs), is designed so as to reduce the probability of blocking, to reduce the area used for signal lines (or routing channels) and overall signal transfer (or routing) effort, to reduce the ratio of parasitic capacitances in relation to the on-resistances of the transfer gates with the aim of reducing the propagation time and the phase shift, respectively, and to reduce dynamic power consumption. These requirements are realized by the concept of (the combination) local and global routing. More specifically, line segments with different lengths in relation to the arrangement of the logic blocks are used, such that there are shorter line segments for connecting only adjacent CLBs and there are longer line segments for connecting clusters of CLBs, wherein shorter and longer line segments lead to a partitioning of the routing into local and global routing. By dividing routing into local and global routing, adjusted line lengths and thus effort-optimized routing can be achieved. FIG. 1 shows a schematic diagram illustrating a configuration for local and global routing in a conventional FPGA. As shown in FIG. 1, local interconnects are provided fo