US-12625835-B2 - Routing traffics having primary and secondary destinations in communication networks

Abstract

Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.

Inventors

• Kevin Safford
• Victor Ruybalid

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260512

Application Date

20240702

Claims (19)

1. 1 . An electronic device comprising: an input port; a primary output port; a secondary output port; and control circuitry configured to: identify a message received via the input port, the message related to debug trace information of a chip; identify a destination identifier in the message; identify a functional state of the secondary output port; if the secondary output port is in a functional state, then identify, based on the destination identifier, whether to output the message via the primary output port or the secondary output port; and if the secondary output port is not in a functional state, then output the message via the primary output port.
2. 2 . The electronic device of claim 1 , wherein the destination identifier is a binary identifier with a first value and a second value.
3. 3 . The electronic device of claim 2 , wherein the destination identifier is a single bit.
4. 4 . The electronic device of claim 2 , wherein the first value indicates that the control circuitry is to output the message via the primary output port, and wherein the second value indicates that the control circuitry is to output the message via the secondary output port.
5. 5 . The electronic device of claim 4 , wherein the control circuitry is configured to output the message via the primary output port if the secondary output port is not in a functional state and the destination identifier is the second value.
6. 6 . The electronic device of claim 1 , wherein the electronic device is an arbiter of a debug trace fabric of the chip.
7. 7 . The electronic device of claim 1 , wherein the secondary output port is not in a functional state if the secondary output port is in a not connected state, a configuration state, or a reset state.
8. 8 . The electronic device of claim 1 , wherein the control circuitry is configured to output the message via the primary output port and the secondary output port without modification to the destination identifier.
9. 9 . One or more non-transitory computer-readable media (NTCRM) comprising instructions that, when executed, are to cause an arbiter of a debug trace fabric of a chip to: identify a message received via an input port of the arbiter; identify a destination identifier in the message; identify a functional state of a secondary output port of the arbiter; if the secondary output port is in a functional state, then identify, based on the destination identifier, whether to output the message via a primary output port of the arbiter or the secondary output port; and if the secondary output port is not in a functional state, then output the message via the primary output port.
10. 10 . The one or more NTCRM of claim 9 , wherein the destination identifier is a binary identifier with a first value and a second value.
11. 11 . The one or more NTCRM of claim 10 , wherein the first value indicates that the arbiter is to output the message via the primary output port, and wherein the second value indicates that the arbiter is to output the message via the secondary output port.
12. 12 . The one or more NTCRM of claim 11 , wherein the arbiter is configured to output the message via the primary port if the secondary output port is not in a functional state and the destination identifier is the second value.
13. 13 . The one or more NTCRM of claim 9 , wherein the secondary output port is not in a functional state if the secondary output port is in a not connected state, a configuration state, or a reset state.
14. 14 . The one or more NTCRM of claim 9 , wherein the arbiter is configured to output the message via the primary output port and the secondary output port without modification to the destination identifier.
15. 15 . A chip comprising: a debug trace fabric encoder configured to generate a message related to debug trace information of the chip, wherein the message includes a destination identifier; and an arbiter configured to: identify the message received from the debug trace fabric encoder via an input port of the arbiter; identify a functional state of a secondary output port of the arbiter; if the secondary output port is in a functional state, then identify, based on the destination identifier, whether to output the message via a primary output port of the arbiter or the secondary output port; and if the secondary output port is not in a functional state, then output the message via the primary output port.
16. 16 . The chip of claim 15 , wherein the destination identifier is a single-bit binary identifier with a first value and a second value.
17. 17 . The chip of claim 16 , wherein the first value indicates that the arbiter is to output the message via the primary output port, and wherein the second value indicates that the arbiter is to output the message via the secondary output port.
18. 18 . The chip of claim 17 , wherein the arbiter is configured to output the message via the primary port if the secondary output port is not in a functional state and the destination identifier is the second value.
19. 19 . The chip of claim 15 , wherein the arbiter is configured to output the message via the primary output port and the secondary output port without modification to the destination identifier.

Description

RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 16/876,902, entitled “ROUTING TRAFFICS HAVING PRIMARY AND SECONDARY DESTINATIONS IN COMMUNICATION NETWORKS” filed on May 18, 2020, and claims priority to the Ser. No. 16/876,902 application. The entire contents of the Ser. No. 16/876,902 application is incorporated herein by reference. FIELD Embodiments of the present disclosure generally relate to the field of communication networks, more particularly, to routing traffics having primary and secondary destinations in communication networks. BACKGROUND The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. A communication network may include multiple communication nodes interconnected together according to a topology to route traffics from sources to destinations. Routing is the process of selecting a path for a traffic in a communication network or between or across multiple networks. For example, a computer network is a digital telecommunications network for sharing resources between nodes, which are computing devices. As another example, a system on chip (SoC) is an integrated circuit (also known as a “chip”) that integrates all or most components of a computer or other electronic system. Building a complex SoC faces an enormous challenge to get a reliable, high performance product to market on time. Embedded debug and trace logic built into the SoC can greatly assist this task. Often the debug and trace logic of a SoC may include a debug trace fabric (DTF) or network to route trace traffics from sources to destinations. For any communication network design, an important consideration is the available bandwidth. Some networks, e.g., a DTF in a SoC, or other networks, may face challenges for routing on the limited bandwidths. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. FIGS. 1(a)-1(c) schematically illustrate examples for routing traffics in a routing network having a set of routing elements, a set of sources, a primary destination, and a set of secondary destinations, according to various embodiments. FIGS. 2(a)-2(b) schematically illustrate an example debug trace fabric (DTF) having a set of arbiters, a set of sources, a primary destination, and a secondary destination in a system on a chip (SoC), according to various embodiments. FIG. 3 schematically illustrates a process for routing traffics in a routing network having a set of routing elements, a set of sources, a primary destination, and a set of secondary destinations, according to various embodiments. FIG. 4 illustrates a storage medium having instructions for practicing methods described with references to FIGS. 1(a)-1(c), 2(a)-2(b) and 3, in accordance with various embodiments. DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of various embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the various embodiments may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the various embodiments with unnecessary detail. A communication network, e.g., a computer network, a debug trace fabric (DTF) for a system on chip (SoC), or other networks, may include multiple communication nodes interconnected together according to a topology to route traffics from sources to destinations. Communication nodes in a communication network may include sources, intermediate nodes or routing nodes, and destinations. A routing network may be a communication network that performs routing function of traffics. In embodiments, a traffic in a communication network may start from a source and have multiple destination nodes, e.g., a primary destination, and one or more secondary destinations. A primary destination node may be a default destination for a traffic. A traffic intended to reach a secondary destination may be routed to the intended secondary destination, or to the primary destination instead while maintaining the desired fun