US-12625836-B2 - System and method for flexibly crossing packets of different protocols

US12625836B2US 12625836 B2US12625836 B2US 12625836B2US-12625836-B2

Abstract

An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.

Inventors

Nima Nikuie
Lijish Remani Bal

Assignees

MICROCHIP TECHNOLOGY INCORPORATED

Dates

Publication Date: 20260512
Application Date: 20240723

Claims (17)

1 . A system, comprising: a first bus interface having a first number of egress lanes; a second bus interface having a second number of egress lanes, wherein the first number of egress lanes is greater than the second number of egress lanes; a second number of egress selectors, each egress selector having an output coupled to an input of one of a first number of egress memories and each egress selector having a plurality of inputs coupled to the first bus interface egress lanes wherein each egress selector may select any one of the first bus egress lanes to output to the input of the corresponding egress memory; and each egress memory having an output to transfer data to one of the second bus egress lanes, a read enable input coupled to a first finite state machine synchronized to a first clock, and a write enable input coupled to a second finite state machine synchronized to a second clock; wherein the first finite state machine controls a select input of each of the egress selectors.
2 . The system of claim 1 , wherein the first bus interface is a Peripheral Component Interconnect Express (PCIe) bus interface and the second bus interface is an Advanced extensible Interface (AXI) bus interface.
3 . The system of claim 1 , comprising: an egress descriptor memory to store header information, the egress descriptor memory having an input coupled to the first bus interface and an output; and a selector to select either the descriptor memory output or an egress memory output to pass to one of the egress lanes of the second bus interface.
4 . The system of claim 1 , comprising an egress descriptor memory to store packet information for egress bus transactions, the packet information comprising an indication of which of the egress memories contains valid data associated with a corresponding packet.
5 . The system of claim 2 , wherein the first finite state machine selects data from a first egress lane of the PCIe bus interface for delivery to the tenth egress memory destined for the tenth egress lane of the AXI bus.
6 . The system of claim 2 , wherein the first bus interface has 10 egress lanes and the second bus interface as 16 egress lanes.
7 . The system of claim 2 , wherein each output of the egress memories is coupled to one lane of the second bus interface.
8 . A system, comprising: a first bus interface having a first number of ingress lanes; a second bus interface having a second number of ingress lanes, wherein the first number of ingress lanes is greater than the second number of ingress lanes; a first number of ingress memories, each ingress memory having an input coupled to one of the ingress lanes of the first bus interface, an output, a read enable input coupled to a first finite state machine synchronized to a first clock, a write enable input coupled to a second finite state machine synchronized to a second clock; and a second number of ingress selectors, each ingress selector having an output coupled to one of the ingress lanes of the second bus interface, each ingress selector having a plurality of inputs including an input for each lane of the first ingress bus; and wherein the second finite state machine controls a select input of each of the plurality of ingress selectors.
9 . The system of claim 8 , wherein the first bus interface is a 16-lane AXI bus interface, the second bus interface is a 10-lane PCIe bus inter.
10 . The system of claim 8 , comprising: an ingress descriptor memory to store header information, the ingress descriptor memory having an input coupled to the first bus interface and an output, wherein each of the second number of ingress selectors has an input coupled to the ingress descriptor memory output.
11 . The system of claim 8 , comprising an ingress descriptor memory to store packet information for ingress bus transactions, the packet information comprising an indication of which of the ingress memories contains valid data associated with a corresponding packet.
12 . The system of claim 9 , wherein the second finite state machine selects data from the eleventh ingress memory to output to the first ingress lane of the second bus interface.
13 . A method, comprising: at a first time synchronized with a first bus clock: receiving a set of data units of a first ingress packet from a plurality of ingress lanes of a first bus, respective ones of the plurality of ingress lanes providing a respective one of the set of data units, storing each data unit in a respective ingress memory, the number of ingress memories equal to the number of the plurality of ingress lanes, writing a first descriptor to an ingress descriptor memory, the descriptor including an identification of valid data units in the received packet; and at a second time synchronized with a second bus clock: reading the first descriptor from the ingress descriptor memory, and for each of a plurality of valid data units identified in the first descriptor: select the ingress memory containing the respective valid data unit, route the respective valid data unit to one of a plurality of ingress lanes of a second bus, and assert a read enable on the ingress memory containing the respective valid data unit.
14 . The method of claim 13 , comprising: determining the first descriptor identifies more valid data units than ingress lanes in the second bus and identifying remaining valid data units not transferred at the second time, and at a third time synchronized with the second bus clock: for each of the remaining valid data units identified in the first descriptor: select the ingress memory containing the respective valid data unit, route the respective valid data unit to one of the plurality of ingress lanes of a second bus, and assert a read enable on the ingress memory containing the respective valid data unit.
15 . The method of claim 13 , comprising writing an ingress header to an ingress lane of the second bus.
16 . The method of claim 13 , wherein each of the ingress memories is a strip of RAM memory.
17 . The method of claim 14 , wherein: the first bus has a 16 lane bus interface, the second bus has a 10 bus interface, at the second time, the plurality of valid data units are transferred to the second bus, and at the third time, the remaining valid data units are transferred to six lanes of the second bus.

Description

RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 17/973,894 filed on Oct. 26, 2022, which claims priority to commonly owned U.S. Provisional Patent Application No. 63/273,199 filed Oct. 29, 2021, the entire contents of which applications are hereby incorporated by reference for all purposes. FIELD OF THE INVENTION The present application relates to systems and methods for transferring packets between two computer busses. BACKGROUND Computing systems may interface with busses of different protocols and bus sizes to accommodate design choices and available components. The two different busses may not be directly compatible as they may have different timing, protocols, and bus widths, without limitation. There is a need to translate packets from one bus into packets on a second bus. Further, there is a need to reduce gate count and complexity. One approach might utilize a dual-port random access memory (RAM) for each direction in conjunction with sets of registers/flops and barrel shifters. This approach is complex and incorporates far more gates than required in the presently disclosed approach. SUMMARY Examples of the present disclosure include an apparatus for coupling a first and a second data bus. The first bus interface has a first number of egress lanes and a first number of ingress lanes wherein the first number of egress lanes is less than the first number of ingress lanes. The second bus interface has a second number of egress lanes and a second number of ingress lanes. A plurality of egress selectors each has an output coupled to an input of one of a plurality of egress memories and each egress selector has a plurality of inputs coupled to the first bus interfaces ingress lanes wherein each egress selector may select any one of the first bus ingress lanes to output to the input of the corresponding egress memory. Each egress memory has an output coupled to one of the second bus egress lanes, a read enable input coupled to a first finite state machine synchronized to a first clock, and a write enable input coupled to a second finite state machine synchronized to a second clock. A plurality of ingress selectors each has an output coupled to one of the first bus ingress lanes and each ingress selector having a plurality of inputs coupled to the ingress memories wherein each ingress selector may select the output of any one of the ingress memories to output to the corresponding first bus ingress lane. Each ingress memory has an input coupled to one of the second bus ingress lanes, a write enable input coupled to a third finite state machine synchronized to the second clock, and a read enable input coupled to a fourth finite state machine synchronized to the first clock. The first finite state machine controls a select input of each of the egress selectors and the fourth finite state machine controls a select input of each of the ingress selectors. In some examples, the first bus interface is a 10 lane Peripheral Component Interconnect Express (PCIe) bus interface and the second bus interface is a 16 lane Advanced extensible Interface (AXI) bus interface. In some examples, the first finite state machine selects data from a first lane of the PCIe bus interface for delivery to the tenth egress memory destined for the tenth lane of the AXI bus. In some examples, the first bus interface includes 10 egress lanes and 10 ingress lanes. In some examples, the fourth finite state machine selects the first of the egress memories in one data transfer on the first bus ingress lanes and selects the other seven ingress memories in the next data transfer on the first bus ingress lanes. In some examples, each of the ingress and egress memories is a strip of RAM memory. In some examples, the apparatus includes an ingress descriptor memory to store packet information for ingress bus transactions, the packet information comprising an indication of which of the ingress memories contains valid data associated with a corresponding packet. In some examples, the fourth finite state machine tracks which of the ingress memories has data remaining to be transferred. Examples of the present disclosure include a method comprising at a first time synchronized with a first bus clock, receiving an array of data units of a first egress packet from a plurality of egress lanes of a first bus, storing received data units of the array of data units in a respective one of a plurality of egress memories, and writing a first descriptor to an egress descriptor memory, the descriptor including an identification of valid data units in the received packet. The method includes, at a second time synchronized with a second bus clock, reading the first descriptor from the egress descriptor memory, and for each valid data unit identified in the first descriptor, asserting a read enable on the corresponding egress memory to output the data unit to a corresponding one of a plurality of egress lanes of a second bus. In s