US-12625840-B2 - Interface device and method of operating the same

US12625840B2US 12625840 B2US12625840 B2US 12625840B2US-12625840-B2

Abstract

A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.

Inventors

Dae Sik Park
Byung Cheol KANG
Seung Duk Cho

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260512
Application Date: 20240424
Priority Date: 20200616

Claims (20)

1 . A method of operating an interface device including a first buffer and in communication with another interface device including a second buffer, the method comprising: initializing one or more parameters associated with a data transmission or reception of the interface device; receiving a status information indicating that an overflow or an underflow is generated at the second buffer; adjusting the one or more parameters associated with the data transmission or reception of the interface device based on the status information; and performing the data transmission or reception based on the adjusted one or more parameters.
2 . The method of claim 1 , wherein adjusting the one or more parameters includes adjusting a clock frequency range of a spread spectrum clocking scheme.
3 . The method of claim 2 , wherein adjusting the clock frequency range of the spread spectrum clocking scheme comprises: initializing the clock frequency range based on a fundamental frequency; adjusting the clock frequency range by a predetermined step value; performing the data transmission or reception based on the adjusted clock frequency range; and determining whether a pre-underflow or a pre-overflow is generated in at least one of the first buffer and the second buffer during the data transmission or reception.
4 . The method of claim 3 , further comprising: selecting, upon determination that the pre-underflow or the pre-overflow is generated in the second buffer during the data transmission or reception, a currently applied clock frequency range as the clock frequency range of the spread spectrum clocking scheme.
5 . The method of claim 3 , further comprising: re-adjusting, upon determination that neither the pre-underflow nor the pre-overflow is generated in the second buffer during the data transmission or reception, the clock frequency range by the step value; performing at least one of data transmission or reception based on the adjusted clock frequency range; and determining whether the pre-underflow or the pre-overflow is generated in at least one of the first buffer and the second buffer based on the data transmission or reception.
6 . The method of claim 3 , wherein adjusting the clock frequency range by the step value includes increasing the clock frequency range by the step value.
7 . The method of claim 1 , wherein adjusting the one or more parameters includes determining an interval for inserting a skip ordered-set into the transmission data.
8 . The method of claim 7 , wherein determining the interval for inserting the skip ordered-set into the transmission data comprises: initializing the interval for inserting the skip ordered-set; adjusting the interval by a predetermined step value; and performing the data transmission or reception including the skip ordered-set based on the adjusted interval.
9 . The method of claim 8 , further comprising: determining whether an overflow or an underflow is generated in at least one of the first buffer and the second buffer based on the data transmission or reception; and selecting, upon determination that the overflow or the underflow is generated in the second buffer, a current interval as the interval for inserting the skip ordered-set.
10 . The method of claim 9 , wherein adjusting the interval by the predetermined step value includes increasing the interval by the predetermined step value.
11 . A method of operating an interface device including a first buffer and in communication with another interface device including a second buffer, the method comprising: initializing one or more parameters associated with clock signals for a data transmission or reception of the interface device; adjusting the one or more parameters by a step value; performing at least one of transmission or reception of data to and from the other interface device communicating with the interface device based on the adjusted one or more parameters; receiving, from the other interface device, a status information indicating a status of the second buffer; and determining whether a pre-underflow or a pre-overflow is generated in the second buffer based on the status information.
12 . The method of claim 11 , further comprising: selecting, upon determination that the pre-underflow or the pre-overflow is generated in the second buffer, current one or more parameters as an optimal transmission parameter.
13 . The method of claim 11 , further comprising: re-adjusting, upon determination that neither the pre-underflow nor the pre-overflow is generated in the second buffer during the data transmission or reception, the transmission parameter by the step value; performing at least one of transmission or reception of the data to and from the other interface device based on the adjusted one or more parameters; re-receiving, from the other interface device, the status information indicating a status of the second buffer; and determining whether the pre-underflow or the pre-overflow is generated in the second buffer based on the received status information.
14 . The method of claim 11 , wherein the one or more parameters include a clock frequency range of spread spectrum clocking scheme.
15 . The method of claim 11 , wherein the one or more parameters include an interval for inserting a skip ordered-set into the transmission data.
16 . An interface device comprising: a receiver configured to receive data; a buffer in communication with the receiver and configured to store the received data; a transmitter configured to output skip ordered-sets; wherein the receiver is configured to receive a second status information indicating a status of another buffer included in another interface device; wherein an interval between the skip ordered-sets outputted from the transmitter is derived from a link characteristic; wherein the skip ordered-sets are used to compensate a difference in frequencies between bit rates at two ends of a link.
17 . The interface device of claim 16 , further comprising: a spread spectrum clocking controller configured to control a transmission clock generator and control a clock frequency of a spread spectrum clocking scheme; and a buffer status monitor configured to transfer first status information indicating the status of the buffer to the spread spectrum clocking controller; wherein the buffer transfers the second status information to the spread spectrum clocking controller; and wherein the spread spectrum clocking controller is configured to determine a clock frequency range of a spread spectrum clocking scheme based on the first status information and the second status information.
18 . The interface device of claim 17 , wherein: the spread spectrum clocking controller initializes the clock frequency range based on a fundamental frequency and adjusts the clock frequency range by a step value; the transmitter transmits data based on the adjusted clock frequency range; the receiver receives data from the other interface device; and the spread spectrum clocking controller determines whether a pre-underflow or a pre-overflow is generated in the second buffer based on the first status information and the second status information generated based on a transmission and reception of the data.
19 . The interface device of claim 18 , wherein the spread spectrum clocking controller determines that a current clock frequency range as an optimal clock frequency range, when the pre-underflow or the pre-overflow is generated in the second buffer.
20 . The interface device of claim 18 , wherein when the pre-underflow or the pre-overflow is not generated in the first buffer or the second buffer, the spread spectrum clocking controller re-adjusts the clock frequency range by the step value, the transmitter re-transmits data based on the re-adjusted clock frequency range, the receiver re-receives data from the other interface device, and the spread spectrum clocking controller determines whether the pre-underflow or the pre-overflow is generated in the first buffer or the second buffer based on the first status information and the second status information generated based on the transmission and reception of the data.

Description

CROSS-REFERENCE TO RELATED APPLICATION This patent document is a continuation of, and claims the priority and benefits of, U.S. patent application Ser. No. 17/840,340 filed on Jun. 14, 2022, which is a divisional of, and claims the priority and benefits of, U.S. patent application Ser. No. 17/349,775 filed on Jun. 16, 2021, which claims the priority and benefits of Korean patent application number 10-2020-0073157 filed on Jun. 16, 2020. The entire contents of the above applications are incorporated by reference as part of the disclosure of this patent document. TECHNICAL FIELD The embodiments of the disclosed technology relate to an electronic device, and more particularly, to an interface device and a method of operating the same. BACKGROUND Input/output interface provides a method for transferring information between two or more separate electronic components. Examples of the input/output interface include industry standard architecture (ISA), peripheral component interconnect (PCI), advanced graphics port (AGP), parallel advanced technology attachment (PATA), or serial advanced technology attachment (SATA). Recently, PCI express (PCIe) has been developed to replace the older bus standards. The PCIe has numerous improvements over the older standards, including higher bus bandwidth, less I/O pin number, smaller physical area and higher performance scalability. SUMMARY The embodiments of the disclosed technology provide an interface device capable of adaptively determining a transmission parameter based on a link characteristic. In an embodiment of the disclosed technology, a method of operating an interface device including a first buffer and in communication with another interface device including a second buffer is provided. The method of operating the interface device includes initializing one or more parameters associated with clock signals for a data transmission or reception of the interface device, checking whether the interface device is in a predetermined mode for adjusting the one or more parameters, adjusting, upon determination that the interface device is in the predetermined mode, the one or more parameters associated with the clock signals of the interface device based on how much of the first buffer or the second buffer is filled with data, and performing the data transmission or reception based on the adjusted one or more parameters associated with the clock signals. In an embodiment, adjusting the one or more parameters may include adjusting a clock frequency range of spread spectrum clocking scheme. In an embodiment, adjusting the clock frequency range of the spread spectrum clocking scheme may include initializing the clock frequency range based on a fundamental frequency, adjusting the clock frequency range by a predetermined step value, performing the data transmission or reception based on the adjusted clock frequency range, and determining whether a pre-underflow or a pre-overflow is generated in at least one of the first buffer and the second buffer during the data transmission or reception. In an embodiment, the method may further include selecting, upon determination that the pre-underflow or the pre-overflow is generated in the first buffer or the second buffer during the data transmission or reception, a currently applied clock frequency range as the clock frequency range of the spread spectrum clocking scheme. In an embodiment, the method may further include re-adjusting, upon determination that neither the pre-underflow nor the pre-overflow is generated in at least one of the first buffer or the second buffer during the data transmission or reception, the clock frequency range by the step value, performing at least one of data transmission or reception based on the adjusted clock frequency range, and determining whether the pre-underflow or the pre-overflow is generated in at least one of the first buffer and the elastic buffer based on the data transmission or reception. In an embodiment, adjusting the clock frequency range by the step value may include increasing the clock frequency range by the step value. In an embodiment, adjusting the one or more parameters may include determining an interval for inserting a skip ordered-set into the transmission data. In an embodiment, determining the interval for inserting the skip ordered-set into the transmission data may include initializing the interval for inserting the skip ordered-set, adjusting the interval by a predetermined step value, performing the data transmission or reception including the skip ordered-set based on the adjusted interval, and determining whether a pre-underflow or a pre-overflow is generated in at least one of the first buffer and the second buffer based on the data transmission or reception. In an embodiment, the method may further include selecting, upon determination that the pre-underflow or the pre-overflow is generated in at least one of the first elastic buffer or the second elastic buffer, a curr