US-12625841-B2 - Network controller sideband interface retimer

Abstract

An apparatus with a network controller sideband interface retimer includes a second clock circuit configured to transmit a second clock signal to a NIC. The second clock signal is separate from a first clock signal from a clock connected to a BMC. The apparatus includes a NIC data relay circuit configured to receive data packets from the NIC on a first reduced media independent interface (“RMII”) bus and to transmit the received data packets to the BMC over a second RMII bus. The apparatus includes a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal. The delay is adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid.

Inventors

• Michael Decesaris
• Milton Cobo
• Grason Humphrey
• Eric Li

Assignees

• LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.

Dates

Publication Date

20260512

Application Date

20240507

Claims (20)

1. 1 . An apparatus comprising: a second clock circuit configured to transmit a second clock signal to a network interface card (“NIC”) of a computing device, wherein the second clock signal is separate from a first clock signal from a clock connected to a baseboard management controller (“BMC”) of the computing device; a NIC data relay circuit configured to receive data packets from the NIC on a first reduced media independent interface (“RMII”) bus and to transmit the received data packets to the BMC over a second RMII bus, wherein the received data packets to the BMC are received on an RMII bus separate from a data pathway for data packets transmitted from the NIC to a processor of the computing device; and a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal, the delay adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid, the delay calculated to compensate for propagation delay for a signal pathway from the NIC to the apparatus.
2. 2 . The apparatus of claim 1 , further comprising a delay calibration apparatus comprising: a delay adjustment module configured to adjust the delay to the second clock signal over an adjustment range while reading known responses received from the NIC, each known response from the NIC received in response to the NIC receiving a plurality of identical calibration commands from the BMC, each calibration command configured to elicit the known response from the NIC; a response reader module configured to read each known response received from the NIC and to compare each of the received known responses to an expected response; a valid data module configured to determine an amount of delay associated with each received known response matching the expected response; and a delay setting module configured to set the delay of the delayed second clock signal to a value within a valid signal range of delay corresponding to received responses matching the expected response, wherein said modules comprise one or more of hardware circuits, a programmable hardware device, and code executable on a processor, the code stored on one or more computer readable storage media.
3. 3 . The apparatus of claim 2 , further comprising: a signal calibration module configured to cause the BMC repeatedly transmit the calibration command to the NIC; and a calibration termination module configured to cause the BMC to stop transmission of the calibration command to the NIC in response to the delay setting module setting the delay of the delayed second clock signal.
4. 4 . The apparatus of claim 3 , further comprising a delay calibration trigger module configured to direct the signal calibration module to cause the BMC to transmit the calibration command in response to a user command, a hardware testing procedure, a system reboot, a system power on event, and/or detecting installation and/or power on of the NIC, the BMC, and/or the apparatus.
5. 5 . The apparatus of claim 2 , wherein the delay setting module sets the delay in a middle of the valid signal range.
6. 6 . The apparatus of claim 1 , wherein the second clock circuit is further configured to receive the first clock signal from a clock connected to the BMC and wherein the second clock signal is synchronized with the first clock signal.
7. 7 . The apparatus of claim 1 , wherein the RMII bus uses a network controller sideband interface (“NC-SI”) protocol.
8. 8 . The apparatus of claim 1 , further comprising a BMC data relay circuit configured to receive data packets from the BMC and to relay the received data packets from the BMC to the NIC.
9. 9 . The apparatus of claim 1 , wherein the apparatus is configured on a card configured to insert into an open configuration project (“OCP”) slot of a computing device comprising the BMC and the NIC.
10. 10 . The apparatus of claim 1 , wherein: the delay is a first delay, the delayed second clock signal is a first delayed second clock signal, and the NIC is a first NIC, and wherein: the second clock circuit is further configured to transmit the second clock signal to a second NIC; the NIC data relay circuit is further configured to receive data packets from the second NIC on a third RMII bus; and the clock delay circuit is further configured to add a second delay to the second clock signal to create a second delayed clock signal, the second delay adjusted to cause the second delayed clock signal to coincide with a time during receipt of data packets received from the second NIC when data of each bit of the data packets received from the second NIC is valid; and/or the clock delay circuit is further configured to add a third delay to the second clock signal to create a third delayed clock signal, the third delay adjusted to cause the third delayed clock signal to coincide with a time during receipt of data packets from the BMC when data of each bit of the data packets received from the BMC is valid.
11. 11 . A method comprising: transmitting a second clock signal to a network interface card (“NIC”) of a computing device, wherein the second clock signal is separate from a first clock signal from a clock connected to a baseboard management controller (“BMC”) of the computing device; receiving data packets from the NIC on a first reduced media independent interface (“RMII”) bus, wherein the received data packets to the BMC are received on an RMII bus separate from a data pathway for data packets transmitted from the NIC to a processor of the computing device; adding a delay to the second clock signal to create a delayed second clock signal, the delay adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid, the delay calculated to compensate for propagation delay for a signal pathway from the NIC to the apparatus; and transmitting the received data packets to the BMC over a second RMII bus.
12. 12 . The method of claim 11 , further comprising: adjusting the delay to the second clock signal over an adjustment range while reading known responses received from the NIC, each known response from the NIC received in response to the NIC receiving a plurality of identical calibration commands from the BMC, each calibration command configured to elicit the known response from the NIC; reading each known response received from the NIC; comparing each of the received known responses to an expected response; determining an amount of delay associated with each received known response matching the expected response; and setting the delay of the delayed second clock signal to a value within a valid signal range of delay corresponding to received responses matching the expected response.
13. 13 . The method of claim 12 , further comprising: causing the BMC to start repeatedly transmitting the calibration command to the NIC; and causing the BMC to stop transmission of the calibration command to the NIC in response to setting the delay of the delayed second clock signal.
14. 14 . The method of claim 13 , wherein causing the BMC to repeatedly transmit the calibration command to the NIC is in response to a user command, a hardware testing procedure, a system reboot, a system power on event, and/or detecting installation and/or power on of the NIC, the BMC, and/or a computing device comprising the BMC and NIC.
15. 15 . The method of claim 11 , wherein the RMII bus uses a network controller sideband interface (“NC-SI”) protocol.
16. 16 . The method of claim 11 , further comprising: prior to transmitting the second clock signal: receiving the first clock signal from a clock connected to the BMC; synchronizing the second clock signal with the first clock signal; receiving data packets from the BMC; and relaying the received data packets from the BMC to the NIC.
17. 17 . The method of claim 11 , wherein an apparatus comprising the method is configured on a card configured to insert into an open configuration project (“OCP”) slot of a computing device comprising the BMC and the NIC.
18. 18 . A computing device comprising: a processor; a network interface card (“NIC”); a baseboard management controller (“BMC”); a second clock circuit configured to transmit a second clock signal to the NIC, wherein the second clock signal is separate from a first clock signal from a clock connected to the BMC; a NIC data relay circuit configured to receive data packets from the NIC on a reduced media independent interface (“RMII”) bus and to transmit the received data packets to the BMC over an RMII bus, wherein the received data packets to the BMC are received on an RMII bus separate from a data pathway for data packets transmitted from the NIC to a processor of the computing device; and a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal, the delay adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid, the delay calculated to compensate for propagation delay for a signal pathway from the NIC to the apparatus, wherein said circuits comprise one or more of hardware circuits, a programmable hardware device, and code executable on a processor, the code stored on one or more computer readable storage media.
19. 19 . The computing device of claim 18 , further comprising a delay calibration apparatus comprising: a delay adjustment module configured to adjust the delay to the second clock signal over an adjustment range while reading known responses received from the NIC, each known response from the NIC received in response to the NIC receiving a plurality of identical calibration commands from the BMC, each calibration command configured to elicit the known response from the NIC; a response reader module configured to read each known response received from the NIC and to compare each of the received known responses to an expected response; a valid data module configured to determine an amount of delay associated with each received known response matching the expected response; and a delay setting module configured to set the delay of the delayed second clock signal to a value within a valid signal range of delay corresponding to received responses matching the expected response, wherein said modules comprise one or more of hardware circuits, a programmable hardware device, and code executable on a processor, the code stored on one or more computer readable storage media.
20. 20 . The computing device of claim 18 , wherein: the RMII bus uses a network controller sideband interface (“NC-SI”) protocol; an apparatus comprising the second clock circuit, the NIC data relay circuit, and the clock delay circuit is configured on a card configured to insert into an open configuration project (“OCP”) slot of a computing device comprising the BMC and the NIC; and/or prior to transmitting the second clock signal, the second clock circuit is further configured to receive the first clock signal from a clock connected to the BMC and to synchronize the second clock signal with the first clock signal, and further comprising a BMC data relay circuit configured to receive data packets from the BMC and to relay the received data packets from the BMC to the NIC.

Description

FIELD The subject matter disclosed herein relates to extending a clock signal and more particularly relates to extending and synchronizing a clock signal for signals between a management controller and a network interface card. BACKGROUND In some architectures of computing devices that include a baseboard management controller (“BMC”), cabling from the BMC to a network interface card (“NIC”) is long enough so that propagation delay affects data validity of communications between the BMC and the NIC. BRIEF SUMMARY An apparatus with a network controller sideband interface retimer is disclosed. A method and computing device also include the functions of the apparatus. The apparatus includes a second clock circuit configured to transmit a second clock signal to a NIC. The second clock signal is separate from a first clock signal from a clock connected to a BMC. The apparatus includes a NIC data relay circuit configured to receive data packets from the NIC on a first reduced media independent interface (“RMII”) bus and to transmit the received data packets to the BMC over a second RMII bus. The apparatus includes a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal. The delay is adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid. A method includes transmitting a second clock signal to a NIC. The second clock signal is separate from a first clock signal from a clock connected to a BMC. The method includes receiving data packets from the NIC on a first RMII bus and adding a delay to the second clock signal to create a delayed second clock signal. The delay is adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid. The method includes transmitting the received data packets to the BMC over a second RMII bus. A computing device includes a processor, a NIC, a BMC, and a second clock circuit configured to transmit a second clock signal to the NIC. The second clock signal is separate from a first clock signal from a clock connected to the BMC. The computing device includes a NIC data relay circuit configured to receive data packets from the NIC on a RMII bus and to transmit the received data packets to the BMC over an RMII bus, and a clock delay circuit configured to add a delay to the second clock signal to create a delayed second clock signal. The delay is adjusted to cause the delayed second clock signal to coincide with a time during receipt of the data packets received from the NIC when data of a bit of the data packets received from the NIC is valid. The circuits include one or more of hardware circuits, a programmable hardware device, and code executable on a processor. The code is stored on one or more computer readable storage media. BRIEF DESCRIPTION OF THE DRAWINGS A more particular description of the embodiments briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Understanding that these drawings depict only some embodiments and are not therefore to be considered to be limiting of scope, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which: FIG. 1A is a schematic block diagram illustrating a system with a network controller sideband interface retimer, according to various embodiments; FIG. 1B is a schematic block diagram illustrating a system with a network controller sideband interface retimer and a NIC in an open configuration project (“OCP”) slot, according to various embodiments; FIG. 2 is a schematic block diagram illustrating an apparatus for a network controller sideband interface retimer, according to various embodiments; FIG. 3 is a schematic block diagram illustrating another apparatus for a network controller sideband interface retimer, according to various embodiments; FIG. 4A is a schematic block diagram illustrating a circuit for a network controller sideband interface retimer, according to various embodiments; FIG. 4B is a schematic block diagram illustrating a circuit for a network controller sideband interface retimer for two NICs connected with cables of different lengths, according to various embodiments; FIG. 4C is a schematic block diagram illustrating a circuit for a network controller sideband interface retimer, for two NICs connected with cables of different lengths and variable cable length to a BMC, according to various embodiments; FIG. 4D is a schematic block diagram illustrating a circuit for an arbitration circuit for a network controller sideband interface retimer, according to various embodiments; FIG. 5 is a schematic flow chart diagram illustrating a method for a n