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US-12625950-B2 - Provisioning of out-of-band (OOB) manageability features in heterogeneous computing platforms

US12625950B2US 12625950 B2US12625950 B2US 12625950B2US-12625950-B2

Abstract

Systems and methods for provisioning of Out-of-Band (OOB) manageability features in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform and an OOB Microcontroller Unit (MCU) integrated into the heterogeneous computing platform or an Embedded Controller (EC) integrated into or coupled to the heterogeneous computing platform, where the OOB MCU or EC is configured to, in response to a status of a flag, enable OOB packet sniffing operations.

Inventors

  • Adolfo S. Montero
  • Abeye Teshome
  • Alok Pant

Assignees

  • DELL PRODUCTS, L.P.

Dates

Publication Date
20260512
Application Date
20230802

Claims (20)

  1. 1 . An Information Handling System (IHS), comprising: a heterogeneous computing platform; and an Out-of-Band (OOB) Microcontroller Unit (MCU) integrated into the heterogeneous computing platform or an Embedded Controller (EC) integrated into or coupled to the heterogeneous computing platform, wherein the OOB MCU or EC is configured to, in response to a status of a flag read from non-volatile memory, enable OOB packet sniffing operations that permit the OOB MCU or EC to perform OOB operations while every IHS host processor remains in a host processor low power state, wherein the OOB operations comprise: receive an OOB packet; choose, from a plurality of crypto devices based, at least in part, upon a header of the OOB packet, a selected crypto device to validate the OOB packet; and validate the OOB packet at least in part with the selected crypto device.
  2. 2 . The IHS of claim 1 , wherein the heterogeneous computing platform comprises: a System-On-Chip (SoC), a Field-Programmable Gate Array (FPGA), or an Application-Specific Integrated Circuit (ASIC).
  3. 3 . The IHS of claim 1 , wherein the heterogeneous computing platform comprises a Reduced Instruction Set Computer (RISC) processor and a plurality of devices coupled to an interconnect.
  4. 4 . The IHS of claim 3 , wherein the plurality of devices comprises at least one of: a Graphical Processing Unit (GPU), an audio Digital Signal Processor (aDSP), a sensor hub, a Neural Processing Unit (NPU), a Tensor Processing Unit (TPU), a Neural Network Processor (NNP), an Intelligence Processing Unit (IPU), an Image Signal Processor (ISP), or a Video Processing Unit (VPU).
  5. 5 . The IHS of claim 3 , wherein the interconnect comprises at least one of: an Advanced Microcontroller Bus Architecture (AMBA) bus, a QuickPath Interconnect (QPI) bus, or a HyperTransport (HT) bus.
  6. 6 . The IHS of claim 1 , wherein the status indicates a first power on event recorded by a Basic Input/Output System (BIOS).
  7. 7 . The IHS of claim 1 , wherein the status indicates that the IHS is in, or not in, a shipping mode.
  8. 8 . The IHS of claim 1 , wherein to enable the OOB packet sniffing operations, the OOB MCU or EC is configured to: wake up from a low-power state while a host processor of the heterogeneous computing platform remains in the low-power state; and wake up a network device configured to access a cloud service through an OOB channel to check a status of an OOB command buffer while the host processor remains in the low-power state.
  9. 9 . The IHS of claim 8 , wherein the low-power state comprises an Advanced Configuration and Power Interface (ACPI) G3 state.
  10. 10 . The IHS of claim 8 , where the OOB MCU or the EC comprises a Real-Time Clock (RTC) timer powered by an RTC battery when the IHS is in a low-power state.
  11. 11 . The IHS of claim 10 , wherein the OOB MCU or the EC comprises an RTC wake circuit coupled to the RTC timer, wherein the OOB MCU or the EC is configured to switch from the RTC battery to an always-on voltage bus upon expiration of the RTC timer, and wherein the always-on voltage bus enables the OOB MCU or the EC to wake up from the low-power state.
  12. 12 . The IHS of claim 11 , wherein the OOB MCU or the EC is configured to control a switch to wake up the network device from the low-power state.
  13. 13 . An Out-of-Band (OOB) Microcontroller Unit (MCU) or Embedded Controller (EC) integrated into or coupled to a heterogeneous computing platform of an Information Handling System (IHS), the OOB MCU or EC comprising: a processing core distinct from any host processor of the heterogeneous computing platform; and a memory coupled to the processing core, the memory having program instructions stored thereon that, upon execution by the processing core, cause the OOB MCU or EC to: check a status of a flag read from non-volatile memory; and enable or disable OOB packet sniffing operations based, at least in part, upon the status, wherein enable OOB packet sniffing operations permits the OOB MCU or EC to perform OOB operations while every IHS host processor remains in a host processor low power state, wherein the OOB operations comprise: receive an OOB packet; choose, from a plurality of crypto devices based, at least in part, upon a header of the OOB packet, a selected crypto device to validate the OOB packet; individually power the selected crypto device; validate the OOB packet at least in part with the selected crypto device; and remove power from the selected crypto device after validation of the OOB packet is complete.
  14. 14 . The OOB MCU or EC of claim 13 , wherein the status indicates that the IHS has not been provisioned to a customer, and wherein the program instructions, upon execution, cause the OOB MCU or EC to disable OOB packet sniffing operations.
  15. 15 . The OOB MCU or EC of claim 13 , wherein the status indicates that the IHS is being shipped to a customer, and wherein the program instructions, upon execution, cause the OOB MCU or EC to disable OOB packet sniffing operations.
  16. 16 . In an Information Handling System (IHS) comprising a heterogeneous computing platform and an Out-of-Band (OOB) Microcontroller Unit (MCU) integrated into the heterogeneous computing platform or an Embedded Controller (EC) integrated into or coupled to the heterogeneous computing platform, a method comprising: checking a status of a flag read from non-volatile memory; and enabling OOB packet sniffing operations, at least in part, based upon the status, wherein enabling OOB packet sniffing operations permits the OOB MCU or EC to perform OOB operations while every IHS host processor remains in a host processor low power state, wherein the OOB operations comprise: receiving an OOB packet; choosing, from a plurality of crypto devices based, at least in part, upon a header of the OOB packet, a selected crypto device to validate the OOB packet; individually powering the selected crypto device; validating the OOB packet at least in part with the selected crypto device; in response to determining the OOB packet comprises a local storage wipe command, performing at least one additional authentication operation on the OOB packet, based at least in part on elliptic-curve cryptography; and removing power from the selected crypto device after validation of the OOB packet is complete.
  17. 17 . The method of claim 16 , wherein the status indicates that the IHS has been provisioned to a customer.
  18. 18 . The method of claim 16 , wherein the status indicates a first power on event.
  19. 19 . The method of claim 16 , wherein the status indicates a presence of an encryption key or digital certificate.
  20. 20 . The method of claim 16 , wherein the status indicates that the IHS is not in a shipping mode.

Description

FIELD This disclosure relates generally to Information Handling Systems (IHSs), and more specifically, to systems and methods for provisioning of Out-of-Band (OOB) manageability features in heterogeneous computing platforms. BACKGROUND As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store it. One option available to users is an Information Handling System (IHS). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. Variations in IHSs allow for IHSs to be general or configured for a specific user or specific use, such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems. Historically, IHSs with desktop and laptop form factors have had conventional Operating Systems (OSs) (e.g., WINDOWS, LINUX, MAC OS, etc.) executed on INTEL or AMD's “x86”-type processors. Other types of processors, such as ARM processors, have been used in smartphones and tablet devices, which typically run thinner, simpler, or mobile OSs (e.g., ANDROID, IOS, WINDOWS MOBILE, etc.). More recently, however, IHS manufacturers have started producing full-fledged desktop and laptop IHSs equipped with ARM-based platforms. In fact, certain OSs (e.g., WINDOWS on ARM) have also been developed to provide users with a more quintessential OS experience on those platforms. Devices known as Embedded Controllers (ECs) have played a central role in their overall operation of traditional x86-based platforms. An EC is a microcontroller or processing core mounted on an IHS's motherboard which is configured to manage several critical IHS processes, ranging from early power rail sequencing to power limits and thermal limits, and to provide low-level hardware controls via a myriad of General-Purpose Input/Outputs (GPIOs). The EC is also responsible for facilitating Out-of-Band (OOB) management of its IHS. OOB management involves the use of dedicated interfaces for accessing and managing aspects of an IHS from a remote location, through a plane separate from the production network. As the inventors hereof have recognized, however, ARM-based platforms currently lack ECs (or other microcontrollers) usable to support OOB management. SUMMARY Systems and methods for provisioning of Out-of-Band (OOB) manageability features in heterogeneous computing platforms are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a heterogeneous computing platform and an OOB Microcontroller Unit (MCU) integrated into the heterogeneous computing platform or an Embedded Controller (EC) integrated into or coupled to the heterogeneous computing platform, where the OOB MCU or EC is configured to, in response to a status of a flag, enable OOB packet sniffing operations. For example, the heterogeneous computing platform may include: a System-On-Chip (SoC), a Field-Programmable Gate Array (FPGA), or an Application-Specific Integrated Circuit (ASIC). The heterogeneous computing platform may include a Reduced Instruction Set Computer (RISC) processor and a plurality of devices coupled to an interconnect. The plurality of devices may include at least one of: a Graphical Processing Unit (GPU), an audio Digital Signal Processor (aDSP), a sensor hub, a Neural Processing Unit (NPU), a Tensor Processing Unit (TPU), a Neural Network Processor (NNP), an Intelligence Processing Unit (IPU), an Image Signal Processor (ISP), or a Video Processing Unit (VPU). And the interconnect may include at least one of: an Advanced Microcontroller Bus Architecture (AMBA) bus, a QuickPath Interconnect (QPI) bus, or a HyperTransport (HT) bus. The status may indicate a first power on event recorded by a Basic Input/Output System (BIOS). Additionally, or alternatively, the status may indicate that the IHS is in not in a shipping mode. To enable the OOB packet sniffing operations, the OOB MCU or EC may be configured to: wake up from a low-power state while a host processor of the heterogeneous computing platform remains in the low-power state; and wake up a network device configured to access a cloud service through an OOB channel to check a status of an OOB command buffer while the host processor remains in the low-po