US-12626026-B2 - Methods and apparatus to prevent a false disconnection in universal serial bus devices

US12626026B2US 12626026 B2US12626026 B2US 12626026B2US-12626026-B2

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to prevent a false disconnection in universal serial bus devices. An example apparatus includes a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first connectional terminal, the second input terminal coupled to a second connection terminal; filter circuitry including an input terminal and an output terminal, the input terminal coupled to the output terminal of the comparator; a switch including a control terminal, a first current terminal, and a second current terminal, the control terminal coupled to the output terminal of the filter circuitry; and a current source including a first terminal and a second terminal, the first terminal coupled to at least one of the first connection terminal or the second connection terminal, the second terminal coupled to the first current terminal of the switch.

Inventors

WIN NAING MAUNG
Srijan Rastogi
Bharath Singareddy

Assignees

TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date: 20260512
Application Date: 20231129

Claims (20)

1 . An apparatus comprising: a first comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first comparator coupled to a first connection terminal, the second input terminal of the first comparator coupled to a second connection terminal; averaging circuitry including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the averaging circuitry coupled to the first connection terminal, the second input terminal of the averaging circuitry coupled to the second connection terminal; a second comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second comparator coupled to the output terminal of the averaging circuitry, the second input terminal of the second comparator coupled to a threshold voltage terminal; filter circuitry including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the filter circuitry coupled to the output terminal of the first comparator, the second input terminal of the filter circuitry coupled to the output terminal of the second comparator; a transistor including a control terminal, a first current terminal, and a second current terminal, the control terminal of the transistor coupled to the output terminal of the filter circuitry, the first current terminal of the transistor coupled to the first connection terminal, the second current terminal of the transistor coupled to a ground terminal; and a resistor coupling the first connection terminal to the first current terminal of the transistor.
2 . The apparatus of claim 1 , wherein the first and second connection terminals are structured to be coupled to a channel between a first Universal Serial Bus (USB) device and a second USB device.
3 . The apparatus of claim 2 , wherein the first USB device is a host USB device and the second USB device is a peripheral USB device.
4 . The apparatus of claim 1 , further including a voltage source, the first input terminal of the first comparator coupled to the first connection terminal via the voltage source.
5 . The apparatus of claim 1 , the averaging circuitry including: summing circuitry including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the summing circuitry coupled to the first connection terminal, the second input terminal of the summing circuitry coupled to the second connection terminal; and division circuitry including an input terminal and an output terminal, the input terminal of the division circuitry coupled to the output terminal of the summing circuitry, the output terminal of the division circuitry coupled to the first input terminal of the second comparator.
6 . The apparatus of claim 1 , wherein the resistor is a first resistor, and the transistor is a first transistor, the filter circuitry including: inverter circuitry including an input terminal and an output terminal, the input terminal of the inverter circuitry coupled to the output terminal of the first comparator; a second transistor including a control terminal, a first current terminal, and a second current terminal, the control terminal coupled to the output terminal of the inverter circuitry, the first current terminal coupled to a supply voltage terminal; a second resistor including a first terminal and a second terminal, the first terminal of the second resistor coupled to the second current terminal of the second transistor; a capacitor including a first terminal and a second terminal, the first terminal of the capacitor coupled to the second terminal of the second resistor, the second terminal of the capacitor coupled to ground; and a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the second terminal of the second resistor and the first terminal of the capacitor, the output terminal of the buffer coupled to the control terminal of the first transistor.
7 . The apparatus of claim 1 , wherein the filter circuitry is first filter circuitry, the transistor is a first transistor, and the resistor is a first resistor, the apparatus further comprising: a third comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the third comparator coupled to the second connection terminal, the second input terminal of the third comparator coupled to the first connection terminal; second filter circuitry including an input terminal and an output terminal, the first input terminal of the second filter circuitry coupled to the output terminal of the third comparator; a second transistor including a control terminal, a first current terminal, and a second current terminal, the control terminal of the second transistor coupled to the output terminal of the second filter circuitry, the first current terminal of the second transistor coupled to the second connection terminal, the second current terminal of the second transistor coupled to a ground terminal; and a second resistor coupling the second connection terminal to the first current terminal of the second transistor.
8 . The apparatus of claim 7 , further comprising: a first voltage source coupling the second input terminal of the first comparator to the second connection terminal; and a second voltage source coupling the second input terminal of the third comparator to the first connection terminal.
9 . The apparatus of claim 7 , wherein the input terminal of the second filter circuitry is a first input terminal of the second filter circuitry, the second filter circuitry further including a second input terminal coupled to the output terminal of the second comparator.
10 . An apparatus comprising: a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a first connection terminal, the second input terminal of the comparator coupled to a second connection terminal, the first connection terminal and the second connection terminal structured to be coupled to a first universal serial bus (USB) device and a second USB device; a first transistor including a control terminal, a first current terminal, and a second current terminal, the control terminal of the first transistor coupled to the output terminal of the comparator, the first current terminal of the first transistor coupled to a supply voltage terminal; a capacitor including a first terminal and a second terminal, the first terminal of the capacitor coupled to the second current terminal of the first transistor, the second terminal of the capacitor coupled to ground; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the second current terminal of the first transistor and the first terminal of the capacitor; a first resistor coupling the second current terminal of the first transistor to the first terminal of the capacitor and the input terminal of the buffer; a second transistor including a control terminal, a first current terminal, and a second current terminal, the control terminal of the second transistor coupled to the output terminal of the buffer, the first current terminal of the second transistor coupled to the first connection terminal, the second current terminal of the second transistor coupled to a ground terminal; and a second resistor coupling the first connection terminal to the first current terminal of the second transistor.
11 . The apparatus of claim 10 , wherein the first USB device is a host USB device and the second USB device is a peripheral USB device.
12 . The apparatus of claim 10 , further including a voltage source, the first input terminal of the comparator coupled to the first connection terminal via the voltage source.
13 . The apparatus of claim 10 , further comprising: a third transistor including a control terminal, a first current terminal, and a second current terminal, the first current terminal of the third transistor coupled to the second current terminal of the first transistor, the first terminal of the capacitor, and the input terminal of the buffer, the second current terminal of the third transistor coupled to ground; and end-of-packet determination circuitry including an output terminal, the output terminal of the end-of-packet determination circuitry coupled to the control terminal of the third transistor.
14 . The apparatus of claim 13 , wherein the comparator is a first comparator, the end-of-packet determination circuitry including: summing circuitry including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the summing circuitry coupled to the first connection terminal, the second input terminal of the summing circuitry coupled to the second connection terminal; division circuitry including an input terminal and an output terminal, the input terminal of the division circuitry coupled to the output terminal of the summing circuitry; and a second comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second comparator coupled to the output terminal of the division circuitry, the second input terminal of the second comparator coupled to a voltage source, and the output terminal of the second comparator coupled to the control terminal of the third transistor.
15 . The apparatus of claim 13 , the end-of-packet determination circuitry including an input terminal coupled to the output terminal of the buffer and the control terminal of the second transistor.
16 . A system comprising: a universal serial bus (USB) device including a first terminal and a second terminal, the first terminal structured to be coupled to a second USB device via a first interface of a bus, the second terminal structured to be coupled to the second USB device via a second interface of the bus; and false disconnection prevention circuitry configured to: generate a third voltage in response to a difference between a first voltage corresponding to the first terminal and a second voltage corresponding to the second terminal being greater than a threshold voltage; initiate a timer in response to the third voltage being generated; and enable a transistor to adjust the first voltage in response to the timer reaching a threshold duration of time.
17 . The system of claim 16 , wherein the first voltage is adjusted using the threshold voltage.
18 . The system of claim 16 , the false disconnection prevention circuitry further configured to: generate a fourth voltage in response to the difference between the first voltage and the second voltage being less than the threshold voltage; and reset the timer in response to the fourth voltage being generated.
19 . The system of claim 16 , the threshold voltage being a first threshold voltage, the false disconnection prevention circuitry further configured to: determine an average of the first voltage and the second voltage in response to the transistor being enabled; compare the average of the first voltage and the second voltage to a second threshold voltage; and disable the transistor in response to the average of the first voltage and the second voltage being greater than the second threshold voltage.
20 . The system of claim 16 , the false disconnection prevention circuitry further configured to: initiate a counter in response to the transistor being enabled; and disable the transistor in response to the counter reaching a threshold count.

Description

CROSS-REFERENCE TO RELATED APPLICATION This patent application claims the benefit of and priority to U.S. Provisional Patent Application No. 63/525,734, which was filed on Jul. 10, 2023, which is hereby incorporated herein by reference in its entirety. TECHNICAL FIELD This description relates generally to circuits, and, more particularly, to methods and apparatus to prevent a false disconnection in universal serial bus devices. BACKGROUND Universal Serial Bus (USB) devices communicate with each other via a wired connection using a USB protocol. For example, a host USB device may be connected to and/or communicate with a USB peripheral device. The host USB device (e.g., a computer) may include circuitry to determine when the USB peripheral device (e.g., a printer) has been disconnected from the host USB device. The circuitry may generate an alert and/or indication to a user when a USB peripheral device has disconnected from the host USB device. SUMMARY An example of the description includes an apparatus comprising a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a first connectional terminal, the second input terminal coupled to a second connection terminal; filter circuitry including an input terminal and an output terminal, the input terminal of the filter circuitry coupled to the output terminal of the comparator; a switch including a control terminal, a first current terminal, and a second current terminal, the control terminal of the switch coupled to the output terminal of the filter circuitry, the second current terminal of the switch coupled to ground; and a current source including a first terminal and a second terminal, the first terminal of the current source coupled to at least one of the first connection terminal or the second connection terminal, the second terminal of the current source coupled to the first current terminal of the switch. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an example system to implement example false disconnection prevention circuitry in conjunction with two USB devices. FIG. 2 is an example circuit implementation of the example false disconnection prevention circuitry of FIG. 1. FIG. 3 is an example circuit implementation of the filter circuitry 208 of FIG. 2 FIG. 4 is an example circuit implementation of example end-of-packet determination circuitry of FIG. 2. FIG. 5 is a flowchart representative of a method and/or operations that may be executed to implement the false disconnect prevention circuitry of FIG. 2. FIG. 6 is a flowchart representative of a method and/or operations that may be executed to implement the false disconnect prevention circuitry of FIG. 2. The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features. DETAILED DESCRIPTION The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or like parts. Although the drawings show regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended and/or irregular. Universal Serial Bus (USB) devices connected together communicate with each other via a USB protocol. For example, a host USB device (e.g., implemented in a computer) can be connected to and communicate with a USB peripheral device (e.g., a keyboard, a mouse, a sensor, user interface, etc.) based on a USB protocol. In some examples, the host USB device can be connected to the USB peripheral device via a bus including a pair of connections (e.g., wires, cables, etc.) that make up a USB channel. The USB devices transmit and/or receive data using a differential signal that is transmitted via the pair of connections in a USB channel. For example, when two USB devices are connected via a USB channel, the impedance of the pair of connections corresponds to a first resistance. However, if one or both of the connections are disconnected, the impedance will increase, thereby causing the voltage differential (e.g., also referred to as voltage swing) between the two connection pairs to increase. Thus, some host USB devices include circuitry that monitors the voltage differential between the two connections in the pair to identify when the USB peripheral device has disconnected from the host USB device. For example, the host USB device may include an envelope detector to determine when the USB peripheral device has disconnected based on the voltage swing increasing above a threshold amount. The host USB device can perform one or more operations, including sending an alert to a user, when a disconnect is identified. After connected, the USB devices can communicate with each other using data packets sent on the differential pair of connections. According to the USB protocol, some