US-12626039-B1 - Associating physical design metrics of a circuit design with register transfer level representations of the circuit design

Abstract

Design metrics from the physical design of an integrated circuit are made available to the front end designer. Physical design metrics are computed for sub-circuits from the physical design of an integrated circuit. Examples of physical design metrics include metrics for timing, congestion, power consumption and other metrics that depend on physical aspects of the circuit. Correspondence between the sub-circuits and register transfer level (RTL) source elements from RTL source code for the integrated circuit are determined. Examples of RTL source elements include individual lines of RTL source code, modules in the RTL source code, and user-defined constructs in the RTL source code. For different RTL source elements, the physical design metrics for the corresponding sub-circuits are aggregated. These aggregated physical design metrics, including the associations to the corresponding RTL source elements, are made available to users, for example front end designers.

Inventors

• Balkrishna Ramchandra Rashingkar
• Andrew Saunders
• Douglas Chang
• Jeffrey Jude Loescher
• Oliver Werner Kozber
• Liang Tao
• Soumitra Majumder
• Colin Williams

Assignees

• SYNOPSYS, INC

Dates

Publication Date

20260512

Application Date

20220923

Claims (19)

1. 1 . A method, comprising: accessing physical design metrics for sub-circuits from a physical design of an integrated circuit, wherein the physical design includes a layout level design and the physical design metrics are metrics that depend on the layout level design; determining a mapping of which sub-circuits correspond to which register transfer level (RTL) source elements, wherein the RTL source elements are portions of an RTL source code for the integrated circuit; for each RTL source element, aggregating, by a processing device, the physical design metrics for the corresponding sub-circuits according to the mapping; and displaying, on a user interface, the aggregated physical design metrics and corresponding RTL source elements, in a manner that associates the aggregated physical design metrics with the corresponding RTL source elements.
2. 2 . The method of claim 1 , wherein the layout level design includes placement of cells within the layout level design and routing of interconnects between cells.
3. 3 . The method of claim 1 , wherein the RTL source elements comprise individual lines from the RTL source code and modules from the RTL source code.
4. 4 . The method of claim 1 , wherein the RTL source elements comprise user-defined constructs from the RTL source code.
5. 5 . The method of claim 1 , wherein the RTL source elements comprise at least one or more of always@ blocks, while loops, and generate for loops from the RTL source code.
6. 6 . The method of claim 1 , wherein: determining the mapping comprises determining which lines from the RTL source code generate which corresponding cells in the physical design; and aggregating the physical design metrics comprises, for a plurality of individual lines from the RTL source code, aggregating the physical design metrics for the corresponding cells generated by those individual lines.
7. 7 . The method of claim 6 , further comprising: during a design flow to convert the RTL source code to the physical design, tracking the lines from the RTL source code that generate the corresponding cells in the physical design.
8. 8 . The method of claim 6 , wherein the physical design metrics are physical design metrics computed for individual cells in the physical design.
9. 9 . The method of claim 1 , wherein: the RTL source code includes a reference RTL module that is instantiated multiple times in the physical design, and aggregating the physical design metrics comprises, for the reference RTL modules: aggregating the physical design metrics across the multiple instances of the reference RTL module in the physical design.
10. 10 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor device, cause the processor device to: access first metrics from a first design description of an integrated circuit, wherein the first design description includes a layout level design, and the first metrics are dependent on the layout level design; and determine second metrics for a second design description of the integrated circuit, wherein the second design description includes a RTL source code for the integrated circuit without specification of a physical layout of the integrated circuit, and determining the second metrics comprises: determining a mapping of which sub-circuits from the first design description correspond to which register transfer level source elements, wherein the RTL source elements are portions of the RTL source code for the integrated circuit; and aggregating the first metrics for the RTL source elements, based on the mapping between sub-circuits in the first design description and the RTL source elements of the second design description.
11. 11 . The non-transitory computer readable medium of claim 10 , wherein the mapping is a one-to-many mapping from RTL source elements to sub-circuits.
12. 12 . The non-transitory computer readable medium of claim 10 , wherein aggregating the first metrics comprises at least one of summing the first metrics, taking a minimum of the first metrics, taking a maximum of the first metrics and averaging the first metrics.
13. 13 . A system, comprising: a memory storing instructions; and a processor device, coupled with the memory and to execute the instructions, the instructions when executed cause the processor device to display a user interface, the user interface comprising: first elements that display RTL source elements, which are portions of the RTL source code for the integrated circuit; and second elements indicative of aggregated physical design metrics corresponding to the RTL source elements; wherein the aggregated physical design metrics are aggregated from physical design metrics for sub-circuits from a layout level design of the integrated circuit based on a mapping of which sub-circuits correspond to which RTL source elements, the physical design metrics are metrics that depend on the layout level design, and the aggregated physical design metrics and corresponding RTL source elements are displayed in a manner that associates the aggregated physical design metrics with the corresponding RTL source elements.
14. 14 . The system of claim 13 , wherein the physical design metrics are metrics indicative of congestion in the layout level design.
15. 15 . The system of claim 13 , wherein the design metrics are metrics indicative of timing in the layout level design.
16. 16 . The system of claim 13 , wherein the design metrics are metrics indicative of power consumption in the layout level design.
17. 17 . The system of claim 13 , wherein the user interface comprises a table listing the first elements and corresponding second elements.
18. 18 . The system of claim 13 , wherein the first elements comprise a source code listing from the RTL description, and the second elements comprise annotations of the source code indicative of the aggregated physical design metrics.
19. 19 . The system of claim 18 , wherein the annotations are annotations on individual lines of the source code listing.

Description

RELATED APPLICATION This application claims priority under 35 U.S.C. § 119 (e) to U.S. Provisional Patent Application Ser. No. 63/247,732, “Visualizing Physical Design Metrics of a Circuit Design in a Hardware Description Language Representation of the Circuit Design,” filed Sep. 23, 2022. The subject matter of all of the foregoing is incorporated herein by reference in their entirety. TECHNICAL FIELD The present disclosure generally relates to an electronic design automation (EDA) system and, more specifically, to propagating physical design information to register transfer level representations of the circuit design. BACKGROUND Designing a very large scale integrated (VLSI) chip is a complex process that can be divided into two parts: the front end design and the back end design. These two parts of the design process are typically performed using different methods by different designers. The front end designer works on developing a register transfer level (RTL) description of the design, for example using a hardware description language (HDL). The RTL design is synthesized into a gate level netlist. The back end (or physical) designer takes the gate level netlist and works on the physical aspects of the design implementation, including floor-planning, placement, and routing. SUMMARY In certain aspects, design metrics from the physical design are made available to the front end designer. Physical design metrics are computed for sub-circuits from the physical design of an integrated circuit. Examples of physical design metrics include metrics for timing, congestion, power consumption and other metrics that depend on physical aspects of the circuit. Correspondence between the sub-circuits and elements from the RTL source code for the integrated circuit are determined. Examples of RTL source elements include individual lines of RTL source code, modules in the RTL source code and user-defined constructs in the RTL source code. For different RTL source elements, the physical design metrics for the corresponding sub-circuits are aggregated. These aggregated physical design metrics, including the associations to the corresponding RTL source elements, are made available to users, for example to assist in the front end design. Other aspects include components, devices, systems, improvements, methods, processes, applications, computer readable mediums, and other technologies related to any of the above. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the disclosure. The figures are used to provide knowledge and understanding of embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale. FIG. 1 is a flowchart of a process for propagating back end metrics to a front end design, according to an embodiment. FIG. 2 shows a user interface for a design environment for RTL source code according to an embodiment. FIG. 3 shows an RTL hierarchy according to an embodiment. FIG. 4 shows a user interface displaying physical design metrics aggregated over RTL reference modules according to an embodiment. FIG. 5 shows an RTL hierarchy using module constructs according to an embodiment. FIG. 6 shows an RTL hierarchy using reference functions according to an embodiment. FIG. 7 is a flowchart of various processes used during the design and manufacture of an integrated circuit in accordance with some embodiments of the present disclosure. FIG. 8 is a diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure relate to associating physical design metrics of a circuit design with register transfer level (RTL) representations of the circuit design. In a process for designing integrated circuits, front end designers develop register transfer level (RTL) or other functional descriptions of the integrated circuit. They convert these descriptions into a gate-level netlist, using processes such as logical synthesis. Back end designers, also known as physical designers, take the gate-level netlist and develop the physical aspects of the design. Typical processes in the back end design include floorplanning, placement and routing. The resulting physical designs describe the integrated circuit as a set of interconnected circuit blocks, including cells such as may be provided in a cell library. The physical designs may be simulated or otherwise analyzed to compute metrics that depend on the physical design. These are referred to as physical design metrics. For example, timing concerns the time required for signals to propagate from one point in the design to another point and whether that time is consistent with requirements for the integrated circuit. Timing depends on physical aspects of the design, such as the interconnect d