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US-12626040-B1 - Methods and systems for floating node detection

US12626040B1US 12626040 B1US12626040 B1US 12626040B1US-12626040-B1

Abstract

Methods and systems for detecting problematic floating nodes in an electronic circuit or electronic circuit design are presented. Floating node detection methods and systems use graph crawling techniques in combination with machine learning to perform an exhaustive search for floating nodes without requiring the use of expensive commercial simulation tools.

Inventors

  • Indrajit Manna
  • Russell Giles
  • Peter Bell

Assignees

  • DIALOG SEMICONDUCTOR (UK) LIMITED

Dates

Publication Date
20260512
Application Date
20200914

Claims (20)

  1. 1 . A method in an electronic data processing system, a method of optimizing an input circuit design by creating a data structure for transforming the input circuit design, the data structure representing the input circuit design comprising a plurality of nodes connected via edges; and interrogating the data structure to find floating nodes, where each node represents a node of the circuit, each edge represents a circuit component, and wherein the data structure can be traversed across all connected nodes; wherein the plurality of nodes comprises a thousand or more nodes; wherein interrogating the data structure further comprises identifying candidate problematic floating nodes and stimulating each of the identified candidate problematic floating nodes; where said candidate problematic floating nodes are identified as confirmed problematic floating nodes if, when stimulated, a path exists between a high node and a low node as a result of the stimulation and wherein, in response to identifying said candidate problematic floating node to be said confirmed problematic node, apply a proposed fix to rectify the problematic node, and wherein applying the proposed fix comprises tying the problematic node to a first supply connected node or to a second supply connected node; wherein interrogated paths of the data structure are stored in a memory and then have their results referenced in future events instead of the paths being repeated; wherein identifying candidate problematic floating nodes comprises selecting which nodes supply a control signal for a switch device which is selectively operable to control conductivity of a channel; wherein each switch device comprises a first terminal and a second terminal, and for each switch device, the method comprises: tracing a path from the first terminal to the first supply connected node and from the second terminal to the second supply connected node and then identifying a node as a problematic node causing leakage if both paths are found; otherwise, if both paths are not found, tracing a path from a first terminal to the second supply connected node and from a second terminal to the first supply connected node and then if both paths are found, identifying the node as a problematic node causing leakage; and otherwise ignoring/discarding the node from the list of candidate problematic floating nodes.
  2. 2 . The method of claim 1 , wherein the data structure comprises a graph and traversing the data structure comprises crawling the graph.
  3. 3 . The method of claim 1 , further comprising receiving an input circuit design, and transforming the circuit design to said data structure.
  4. 4 . The method of claim 3 , wherein said input circuit design comprises a netlist or other circuit structure description.
  5. 5 . The method of claim 1 , wherein the input further comprises a list of supply connected nodes.
  6. 6 . The method of claim 1 , wherein the data structure comprises a node connectivity representation which comprises any one of: an adjacency matrix, adjacency list, and an edge list.
  7. 7 . The method of claim 3 , wherein the data structure comprises an associative array with unique node names as keys and the value for each key is a connectivity list of component terminals connected to it.
  8. 8 . The method of claim 4 , wherein transforming the circuit design comprises flattening the netlist to a set of primitive circuit components.
  9. 9 . The method of claim 5 , wherein the supply connected nodes comprise at least one high power supply port and at least one low power supply port.
  10. 10 . The method of claim 1 , wherein the input further comprises a list of one or more input ports, wherein each of the input ports can be toggled between two or more input states.
  11. 11 . The method of claim 10 , comprising updating the data structure for different combinations of input states.
  12. 12 . The method of claim 1 , wherein the step of interrogating the data structure to find floating nodes comprises: finding nodes which are not coupled with any supply connected node, and identifying those nodes as said floating nodes.
  13. 13 . The method of claim 12 , wherein identifying nodes which are not connected to any supply connected node comprises: assigning a first test voltage to each node; iteratively propagating a port voltage inside the data structure; and identifying those nodes which remain at the first test voltage after the propagation as nodes not coupled with any supply connected node.
  14. 14 . The method of claim 9 , wherein stimulating each of the identified candidate problematic floating nodes to check if the stimulated node provides a leakage path comprises finding a shortest path in the data structure from the nodes to the supply connected nodes.
  15. 15 . The method of claim 11 , wherein the switch device comprises a transistor.
  16. 16 . The method of claim 2 , wherein, during a data structure traversal, when a diode is encountered, a node adjacent to a first diode electrode is checked to see if it is also coupled with a second diode electrode taking into consideration the expected direction of current flow, were it to be included in a possible leakage path: then, if it is connected, the path search continues; and if it is not connected, the path search aborts.
  17. 17 . The method of claim 12 , wherein interrogating the data structure further comprises identifying combinations of candidate problematic floating nodes, and stimulating each of the identified combinations to check if any of the nodes in the stimulated combination provides a leakage path; where the nodes in the stimulated combination are identified as confirmed problematic floating nodes if a leakage path exists as a result of the stimulation.
  18. 18 . The method of claim 9 , wherein the candidate problematic floating nodes identified as confirmed problematic floating nodes are excluded from a list of candidate floating nodes; and thereafter the method comprises: identifying combinations of the remaining candidate problematic floating nodes, and stimulating each of the identified combinations to check if any of the nodes in the stimulated combination provides a leakage path; where the nodes in the stimulated combination are identified as confirmed problematic floating nodes if a leakage path exists as a result of the stimulation.
  19. 19 . The method of claim 18 , comprising iteratively identifying confirmed problematic floating nodes based on successive new combinations.
  20. 20 . The method of claim 19 , wherein a combination of the remaining candidate problematic floating nodes is selected based on its adjacency to a previously identified node or combination of nodes.

Description

TECHNICAL FIELD The present disclosure relates to methods and systems for floating node detection, and in particular to methods and systems for detecting problematic floating nodes in an electronic circuit or electronic circuit design. BACKGROUND A node of an electric or electronic circuit which is not driven to a defined high or low level is commonly referred to as a floating node. Floating nodes are undesirable in circuits since they can cause problems, such as leakage currents in downstream logic circuits, noise coupling and generally unpredictable and unreliable circuit behaviors. For example, a floating node may, under certain stimulus conditions, provide low-resistance discharge paths between a high (or positive) supply voltage node Vdd and a low (or negative) supply voltage node Vss, resulting in a leakage current. Floating nodes are particularly undesirable if they are coupled a controlling input of a switch, such as the gate of a MOSFET, since they may result in the switch being turned on unintentionally and provide said discharge or leakage paths. Rectification of floating nodes is often expensive in terms of time and money, especially when they are identified late in the design or after silicon is fabricated. Rectifying a floating node identified late in the design process, or which escapes into silicon can often lead to unexpected time delays and costs in production, since it may be necessary to repeat the calibration and characterization of the device, replace mask sets and so on. Therefore, it would be desirable to be able to identify and rectify floating nodes as early as possible. For simple circuits, the use of best design practices which avoid specific structures known to generate floating nodes can be used to ensure that there are no floating nodes. For a long time, peer review was the conventional way of identifying floating nodes in a circuit design. However, manual analysis of each node is clearly not scalable to the number of nodes present in a modern electronic chip, which can comprise nodes in the order of magnitude of thousands or more. There are available some commercial static analytical tools which use circuit topology analyzers to find structures that are likely to result in floating nodes. However, these tools only allow detection of “static” floating nodes; nodes that are physically de-coupled. This is as opposed to “dynamic” nodes which become de-coupled from the power supplies during operation due, for example, to a specific input configuration. Therefore, such static node detection modes can only identify a limited number of cases. Other methods employ complicated simulations to detect both static and dynamic floating nodes, however such methods require building and solving a system of nonlinear differential equations that describe fine behavior of the simulated components. Current state-of-the-art simulation methods to detect floating nodes generally rely on heavy SPICE simulations in which an external voltage or current source is applied at each node, in order to bring it up at or near Vdd/2. If a node has no low-resistance path to Vdd or Vss to clamp the voltage, this will cause a crowbar current to flow in CMOS stage(s) connected to the node and a large leakage current is expected to be detected between Vdd and Vss. While these methods can detect floating nodes, they require extensive setup and simulation cycles and are therefore slow and expensive. Also, due to the complementary nature of NMOS and PMOS transistors, the excitation of floating nodes by external stimulus requires achieving precise mid-rail voltage levels to trigger crowbar currents. This can be a challenging and not always repeatable process. Another significant limitation of the currently available commercial tools is that it can be very challenging to find specific combinations of floating nodes acting together. Many times, a single floating node acting alone may not cause a leakage current but two or more nodes acting together may open a leakage path. Finding the right combination of floating nodes by simulation in a circuit with many nodes often requires very large number of runs and is, therefore, prohibitively time-consuming and often impossible. All known current simulation tools rely on the description of technology- or process-specific data and require a detailed setup. Moreover, the results of the analysis require manual interpretation and are not exhaustive. In conclusion, current state-of-the-art methods have the disadvantage of being computationally expensive and having long runtimes. There is some flexibility in the tuning of the simulations to trade off the precision of the simulation in favor or execution speed, however this considerably reduces the likelihood of detecting floating nodes correctly. In most cases, these methods tend to return an unacceptably high number of false positives. SUMMARY Although current state-of-the-art simulation-based tools provide very detailed information on