US-12626043-B2 - Automatic test pattern generation to increase coverage in detecting defects in analog circuits

US12626043B2US 12626043 B2US12626043 B2US 12626043B2US-12626043-B2

Abstract

Test patterns are generated to test for a specified defect in an analog circuit by applying a succession of different strategies. Each strategy efficiently determines nominal responses and defect responses of the analog circuit to trial test patterns. The nominal response is a response of the analog circuit without the specified defect, and the defect response is a response of the analog circuit with the specified defect. Test patterns are selected based on differences between the nominal and defect responses.

Inventors

Peilin Jiang
Mayukh Bhattacharya

Assignees

SYNOPSYS, INC.

Dates

Publication Date: 20260512
Application Date: 20221212

Claims (16)

1 . A method comprising: receiving a description of an analog circuit and a specification of a defect that may occur in the analog circuit; and applying, by a processing device, a succession of at least two strategies for determining a test pattern to detect the specified defect, wherein two of the strategies in the succession are based on an AC simulation of the analog circuit and on a transient simulation of the analog circuit, and the strategy based on the AC simulation is applied before the strategy based on the transient simulation, each strategy comprising: determining nominal responses and defect responses of the analog circuit to trial test patterns; wherein the nominal response is a response of the analog circuit without the specified defect, and the defect response is a response of the analog circuit with the specified defect; and selecting one or more of the trial test patterns as the test pattern based on differences between the nominal responses and defect responses for the trial test patterns.
2 . The method of claim 1 , wherein the specified defect is one of an open circuit, a short circuit, and a deviation from a nominal value for a component in the analog circuit; the test pattern comprises one or more waveforms applied to the analog circuit; and the response comprises a value of one or more waveforms produced by the analog circuit in response to the test pattern.
3 . The method of claim 1 , further comprising: after applying the succession of strategies, testing a fabricated analog circuit using one or more of the selected trial test patterns.
4 . The method of claim 1 , wherein each strategy in the succession is more computationally expensive to apply than a prior strategy in the succession.
5 . The method of claim 1 , wherein the strategy based on the AC simulation uses characteristic basis functions.
6 . The method of claim 1 , wherein the strategy based on the transient simulation uses a neural network model of the transient simulation.
7 . The method of claim 1 , wherein another of the strategies in the succession is based on a DC simulation of the analog circuit; and the strategies are applied in succession from the DC simulation strategy to the AC simulation strategy to the transient simulation strategy.
8 . The method of claim 1 , wherein the specification of the defect is determined by an end user.
9 . A system comprising: a memory storing instructions; and a processing device, coupled with the memory and to execute the instructions, the instructions when executed cause the processing device to: receive a description of an analog circuit and a specification of a defect that may occur in the analog circuit; and apply multiple iterations of a strategy to update a test pattern to detect the defect, wherein each iteration comprises: determining nominal responses and defect responses of the analog circuit to trial test patterns that are based on a current candidate test pattern; wherein the nominal response is a response of the analog circuit without the specified defect, and the defect response is a response of the analog circuit with the specified defect; and updating the current candidate test pattern based on the differences between the nominal responses and the defect responses for the trial test patterns; and wherein the test patterns comprise a plurality of variables and applying the multiple iterations comprises: subdividing the variables into subsets; and for at least some iterations, the trial test patterns are generated by varying at least one subset of the subsets of variables.
10 . The system of claim 9 , wherein for each iteration, the trial test patterns randomly sample a vicinity of the current candidate test pattern.
11 . The system of claim 9 , wherein for each iteration, the nominal responses and defect responses of the analog circuit to each trial test pattern are determinable independent of the responses to the other trial test patterns.
12 . The system of claim 9 , wherein for each iteration, updating the current candidate test pattern comprises replacing the current candidate test pattern with the trial test pattern that has a desired difference between its nominal response and its defect response.
13 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processing device, cause the processing device to: receive a description of an analog circuit and a specification of a defect that may occur in the analog circuit; perform alternating current (AC) simulations of the analog circuit to determine nominal responses and defect responses of the analog circuit to trial test patterns; wherein the nominal response is a response of the analog circuit without the specified defect, the defect response is a response of the analog circuit with the specified defect, the AC simulation is implemented in a frequency domain, and a frequency domain response of the analog circuit is based on characteristic basis functions that sample the frequency domain response at basis frequencies and expressing the frequency domain response at other frequencies as a linear combination of the characteristic basis functions; and select one or more of the trial test patterns based on differences between the nominal responses and the defect responses for the trial test patterns.
14 . The non-transitory computer readable medium of claim 13 , wherein selecting one or more of the trial test patterns is based on increasing the difference between the nominal responses and the defect responses.
15 . The non-transitory computer readable medium of claim 13 , wherein selecting one of the trial test patterns comprises selecting the frequency domain responses at the basis frequencies based on increasing the difference between the nominal responses and the defect responses.
16 . The non-transitory computer readable medium of claim 13 , wherein the AC simulation is based on a linear model of a behavior of the analog circuit using a small signal assumption.

Description

TECHNICAL FIELD The present disclosure generally relates to an electrical design automation (EDA) system. In particular, the present disclosure relates to automatic test pattern generation to increase coverage of defects in analog circuits. BACKGROUND Testing for defects is a step in the manufacture of integrated circuits. In some testing scenarios, a test pattern is applied to the circuit under test. The response of the circuit to the test pattern is observed and compared to the expected (nominal) response. Deviations between the observed and nominal responses may indicate a defect in the circuit. In digital circuits, signal values are interpreted as a logic 0 or a logic 1 so a defect is present if a 0 is observed when a 1 is expected or vice versa. Detecting defects in analog circuits is not as well-defined, since the signal values are expected to take a range of values and deviations between observed and nominal will also span a range of values. The ease with which a defect in an analog circuit may be detected depends in part on the test pattern applied to the circuit. In a common approach, randomly generated waveforms are applied as test patterns. However, if a particular defect is hard to detect (e.g., produces a weak deviation from nominal) or requires a specific type of test pattern to detect, then testing based on randomly generated waveforms may not detect this defect. SUMMARY In one aspect, test patterns are generated to test for a specified defect in an analog circuit by applying a succession of different strategies. Each strategy determines nominal responses and defect responses of the analog circuit to trial test patterns. The nominal response is a response of the analog circuit without the specified defect, and the defect response is a response of the analog circuit with the specified defect. Test patterns are selected based on the differences between the nominal and defect responses. For example, one of the strategies may be based on an alternating-current (AC) simulation of the analog circuit and another may be based on a transient (time-based) simulation of the analog circuit. Analog circuits have nonlinear behavior. The AC simulation assumes small signals and linearizes the behavior of the analog circuit based on this assumption. The AC simulation may be sped up by implementing it in the frequency domain and by interpolating the frequency response of the circuit based on a limited number of frequency samples, rather than expressly sampling at all frequencies. The transient simulation is a time-based simulation of the circuit, but it can be computationally expensive. It may be sped up by using a model, such as a machine learning model, of the transient simulation rather than executing the simulation each time required. Other aspects include components, devices, systems, improvements, methods, processes, applications, computer readable mediums, and other technologies related to any of the above. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the disclosure. The figures are used to provide knowledge and understanding of embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale. FIG. 1 is a flow diagram for generating a test pattern according to some embodiments of the disclosure. FIG. 2 is a flow diagram for AC simulation according to some embodiments of the disclosure. FIG. 3 shows the architecture of a neural network autoregressive exogenous model according to some embodiments of the disclosure. FIG. 4 is a flow diagram for generating a test pattern using a neural network model of transient simulation according to some embodiments of the disclosure. FIG. 5A is a flow diagram for generating a test pattern using parallelizable randomization according to some embodiments of the disclosure. FIG. 5B is a pictorial representation that illustrates the flow diagram of FIG. 5A. FIG. 6 is a flow diagram for generating a test pattern by subdividing the test pattern according to some embodiments of the disclosure. FIG. 7 is a flow diagram for generating a test pattern using a succession of different strategies according to some embodiments of the disclosure. FIG. 8 depicts a flowchart of various processes used during the design and manufacture of an integrated circuit in accordance with some embodiments of the present disclosure. FIG. 9 depicts a diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure relate to automatic test pattern generation to increase coverage in detecting defects in analog circuits. To test an analog circuit, a test pattern is applied to the circuit, the response of the circuit to the test pattern is observed and a comparison of the observed and nominal r