US-12626045-B2 - Cell-based signal connectivity between wafer frontside and backside

Abstract

A semiconductor structure includes a first backside metal rail that extends across the structure and a second backside metal rail parallel and adjacent to the first backside metal rail. The first and second backside metal rails bound a first circuit row. The structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. The second and third backside metal rails bound a second circuit row. The structure also includes gate metal pitches, which extend across the structure perpendicular to the backside metal rails. The structure also includes a frontside signal wire above the gate metal pitches; and a signal via that penetrates the structure and connects the backside signal wire to the frontside signal wire.

Inventors

• David Wolpert
• Leon Sigal
• Ruilong Xie
• Nicholas Anthony Lanzillo
• Biswanath Senapati
• Lawrence A. Clevenger

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20221230

Claims (20)

1. 1 . A semiconductor structure comprising: a first backside metal rail that extends across the structure in a first direction; a second backside metal rail that extends across the structure parallel and adjacent to the first backside metal rail, wherein the first and second backside metal rails bound a first circuit row; a backside signal wire that interrupts the second backside metal rail; a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail, wherein the second and third backside metal rails bound a second circuit row; adjacent and parallel gate metal pitches that extend across the structure perpendicular to and above the first, second, and third backside metal rails, wherein the gate metal pitches define a width of a signal transfer cell that occupies the first and second circuit rows; a frontside signal wire that extends across the structure above the gate metal pitches; and a signal via that penetrates the structure perpendicular to the first, second, and third backside metal rails and to the gate metal pitches and that connects the backside signal wire to the frontside signal wire.
2. 2 . The semiconductor structure of claim 1 , wherein the signal via is disposed in a space between two adjacent ones of the gate metal pitches.
3. 3 . The semiconductor structure of claim 1 , further comprising: peripheral vias that penetrate the structure perpendicular to the first, second, and third backside metal rails and to the gate metal pitches and in registry with the first, second, and third backside metal rails at edges of the signal transfer cell, wherein locations of the peripheral vias and the signal via define an X.
4. 4 . The semiconductor structure of claim 1 , further comprising: local interconnects that are disposed vertically between the gate metal pitches and the frontside signal wire and that are electrically connected between the signal via and the frontside signal wire.
5. 5 . The semiconductor structure of claim 4 , further comprising: a signal contact that is electrically connected between the local interconnects and the signal via.
6. 6 . The semiconductor structure of claim 5 , wherein the signal contact extends perpendicular to the first, second, and third backside metal rails.
7. 7 . The semiconductor structure of claim 6 , wherein the signal contact is contained within the signal transfer cell.
8. 8 . The semiconductor structure of claim 1 , further comprising a negative-doped well in the structure, wherein the signal via penetrates the negative-doped well.
9. 9 . The semiconductor structure of claim 1 , wherein lengths of the first, second, and third backside metal rails are in a same plane.
10. 10 . The semiconductor structure of claim 1 , further comprising: a complementary metal-oxide-semiconductor inverter cell that is connected between the second and third backside metal rails, adjacent to the signal transfer cell.
11. 11 . The semiconductor structure of claim 1 , wherein the second backside metal rail is interrupted by cuts at either side of the signal via.
12. 12 . The semiconductor structure of claim 11 , wherein each of the cuts is disposed beyond an edge of the signal transfer cell.
13. 13 . The semiconductor structure of claim 1 , wherein the signal transfer cell is free of logic circuitry.
14. 14 . The semiconductor structure of claim 1 , wherein the signal via is centered in the signal transfer cell.
15. 15 . The semiconductor structure of claim 1 , wherein the frontside signal wire is broken into left, middle, and right segments, wherein the middle segment connects to the signal via in the signal transfer cell while the left and right segments extend outside the signal transfer cell.
16. 16 . The semiconductor structure of claim 15 , wherein portions of the left and right segments of the frontside signal wire extend within the signal transfer cell.
17. 17 . A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of an integrated circuit, wherein the HDL design structure comprises: a first backside metal rail that extends across the structure in a first direction; a second backside metal rail that extends across the structure parallel and adjacent to the first backside metal rail, wherein the first and second backside metal rails bound a first circuit row; a backside signal wire that interrupts the second backside metal rail; a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail, wherein the second and third backside metal rails bound a second circuit row; adjacent and parallel gate metal pitches that extend across the structure perpendicular to and above the first, second, and third backside metal rails, wherein the gate metal pitches define a width of a signal transfer cell that occupies the first and second circuit rows; a frontside signal wire that extends across the structure above the gate metal pitches; and a signal via that penetrates the structure perpendicular to the first, second, and third backside metal rails and to the gate metal pitches and that connects the backside signal wire to the frontside signal wire.
18. 18 . The HDL design structure of claim 17 , wherein the signal via is disposed in a space between two adjacent ones of the gate metal pitches.
19. 19 . The HDL design structure of claim 17 , further comprising: peripheral vias that penetrate the structure perpendicular to the first, second, and third backside metal rails and to the gate metal pitches and in registry with the first, second, and third backside metal rails at edges of the signal transfer cell, wherein locations of the peripheral vias and the signal via define an X.
20. 20 . The HDL design structure of claim 17 , further comprising: local interconnects that are disposed vertically between the gate metal pitches and the frontside signal wire and that are electrically connected between the signal via and the frontside signal wire.

Description

BACKGROUND The present invention relates to the electrical, electronic, and computer arts, and more specifically, to power and signal distribution within very large scale integrated (VLSI) circuits. Historically, VLSI designs have utilized a back end of line (BEOL) power and signal grid, in which the metal layers in between the semiconductor devices and the chip package connections (e.g. controlled-collapse chip connections, or C4s) are used both to provide power and ground connections to the devices as well as signal wires between devices. A relatively recent development in VLSI design involves the additional metallization of the opposite side of the wafer (referred to as the backside of the wafer) as well as the frontside of the wafer. SUMMARY Principles of the invention provide techniques for cell-based signal connectivity between wafer frontside and backside. In one aspect, an exemplary semiconductor structure includes a first backside metal rail that extends across the structure in a first direction; a second backside metal rail, which extends across the structure parallel and adjacent to the first backside metal rail. The first and second backside metal rails bound a first circuit row. The exemplary semiconductor structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. The second and third backside metal rails bound a second circuit row. The exemplary semiconductor structure also includes adjacent and parallel gate metal pitches, which extend across the structure perpendicular to and above the backside metal rails. The gate metal pitches define a width of a signal transfer cell that occupies the first and second circuit rows. The exemplary semiconductor structure also includes a frontside signal wire that extends across the structure above the gate metal pitches; and a signal via that penetrates the structure perpendicular to the metal rails and to the gate metal pitches and that connects the backside signal wire to the frontside signal wire. According to another aspect, an exemplary method for operating an integrated circuit includes transmitting a bias signal through a frontside signal wire of the integrated circuit to a signal via of the integrated circuit; transmitting the bias signal through the signal via to a backside signal wire of the integrated circuit; and transmitting the bias signal from the backside signal wire to a gate of the integrated circuit. In one or more embodiments, the frontside signal wire, the signal via, and the backside signal wire are contained within a signal transfer cell. According to another aspect, an exemplary method for designing an integrated circuit includes laying out a signal transfer cell that includes a frontside signal wire, a signal via, and a backside signal wire; and laying out cells adjacent to the signal transfer cell so that at least the frontside signal wire does not extend beyond the signal transfer cell. In view of the foregoing, techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments provide one or more of: Ability to break frontside and/or backside power rails for signal separation, while still providing reliable power to all components of an integrated circuit. Reduced power signal path length with reduced I2R losses. A set of pertinent process constraints on cell design to provide optimal dimensions for a placeable cell for use with place and route tooling. Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts, in a schematic, a top down (plan) view of a semiconductor structure, according to exemplary embodiments. FIG. 2 depicts, in a schematic, a side view of the semiconductor structure that is shown in FIG. 1. FIG. 3 depicts, in a schematic, a top down (plan) view of another semiconductor structure, according to exemplary embodiments. FIG. 4 depicts, in a flowchart, steps of a method for operating an integrated circuit, according to exemplary embodiments. FIG. 5 depicts, in a flowchart, steps of method for designing an integrated circuit, according to exemplary embodiments. FIG. 6 depicts a computing environment usable in connection with semiconductor design, manufacture, and/or test. FIG. 7 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test; FIG. 8 shows further aspects of IC fabrication from physical design data; and FIG. 9 shows an exemplary high-level Electronic Design Automation (EDA) tool flow. DETAILED DESCRIPTION