US-12626046-B2 - Generating routes for an integrated circuit design with non-preferred direction curvilinear wiring

Abstract

Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Inventors

• Akira Fujimura

Assignees

• D2S, INC.

Dates

Publication Date

20260512

Application Date

20230215

Claims (19)

1. 1 . A method of designing an integrated circuit (IC), the method comprising: using a first router to define a first plurality of curvilinear routes each of which traverses one or more routing layers in a first plurality of routing layers of the IC to connect at least two nodes of the IC, wherein in defining each curvilinear route the first router ensures that each curvilinear route that the first router defines is not longer than a threshold distance; and using a second router to define a second plurality of preferred direction, rectilinear routes each of which traverses one or more routing layers in a second plurality of routing layers to connect at least two nodes of the IC.
2. 2 . The method of claim 1 , wherein the second plurality of routing layers has at least first and second routing layers with first and second preferred routing directions respectively.
3. 3 . The method of claim 2 , wherein each preferred routing direction is a horizontal direction or a vertical direction, and the preferred routing directions of different adjacent layers in the second plurality of layers alternate between horizontal and vertical directions.
4. 4 . The method of claim 2 , wherein each preferred routing direction is a horizontal direction, a vertical direction, or a diagonal direction, and the preferred routing directions of different adjacent layers in the second plurality of layers alternate between horizontal, vertical and diagonal directions.
5. 5 . The method of claim 2 , wherein a preferred routing direction on each layer in the second plurality of layers is the direction that includes at least a threshold percentage of the route segments on that layer.
6. 6 . The method of claim 5 , wherein the threshold percentage is 90% or larger.
7. 7 . The method of claim 1 , wherein: the second plurality of rectilinear routes are for a first set of nets and each rectilinear route in the second plurality of rectilinear routes is longer than the threshold distance; the method further comprises using the second router to define a third plurality of preferred direction, rectilinear routes for a second set of nets that comprise a plurality of nets each of which the first router could not connect through a route traversing the first plurality of routing layers; and each of rectilinear route in the third plurality of rectilinear routes traverses one or more routing layers in the second plurality of routing layers to connect at least two nodes of the IC and is shorter than the threshold distance.
8. 8 . The method of claim 1 , wherein the first router penalizes routes that are longer than the threshold distance to bias against defining routes longer than the threshold distance.
9. 9 . The method of claim 1 , wherein the first router uses a constraint that prevents the routes defined by the first router from being longer than the threshold distance.
10. 10 . The method of claim 1 further comprising using the first router to define a third plurality of rectilinear routes traversing the first plurality of routing layers to connect a third plurality of nodes of the IC.
11. 11 . The method of claim 10 , wherein each rectilinear route traversing the first plurality of routing layers is not longer than the threshold distance.
12. 12 . The method of claim 11 , wherein no route produced by the second router is a curvilinear route with at least one curvilinear segment.
13. 13 . The method of claim 11 , wherein the nodes connected by each route include nodes on a substrate of the IC.
14. 14 . The method of claim 1 , wherein the nodes connected by each route include at least one node on a routing layer of the IC.
15. 15 . The method of claim 1 , wherein the first plurality of routing layers includes routing layers 3 and 4, and the second plurality of routing layers includes routing layers 5 and 6.
16. 16 . The method of claim 1 , wherein the second plurality of routing layers includes routing layers 1 and 2.
17. 17 . The method of claim 1 , wherein the first plurality of routing layers includes routing layers 1 and 2.
18. 18 . The method of claim 17 , wherein the routing layers 1 and 2 each has a plurality of regions with preferred direction rectilinear routes for pre-defined IP (intellectual property) circuit blocks, and using the first router comprises using the first router to define a plurality of curvilinear route segments on the routing layers 1 and 2 between the regions with the preferred direction rectilinear routes for the IP circuit blocks.
19. 19 . A non-transitory machine readable medium storing a program that when executed by at least one processing unit designs an integrated circuit (IC), the program comprising sets of instructions for: using a first router to define a first plurality of curvilinear routes each of which traverses one or more routing layers in a first plurality of routing layers of the IC to connect at least two nodes of the IC, wherein in defining each curvilinear route the first router ensures that each curvilinear route that the first router defines is not longer than a threshold distance; and using a second router to define a second plurality of preferred direction, rectilinear routes each of which traverses one or more routing layers in a second plurality of routing layers to connect at least two nodes of the IC.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application is related to the following applications having a similar specification and figures: U.S. patent application Ser. No. 18/110,332, filed Feb. 15, 2023; U.S. patent application Ser. No. 18/110,334, filed Feb. 15, 2023; U.S. patent application Ser. No. 18/110,336, filed Feb. 15, 2023; U.S. patent application Ser. No. 18/110,338, filed Feb. 15, 2023; U.S. patent application Ser. No. 18/110,343, filed Feb. 15, 2023; U.S. patent application Ser. No. 18/110,344, filed Feb. 15, 2023; U.S. patent application Ser. No. 18/110,345, filed Feb. 15, 2023; U.S. patent application Ser. No. 18/110,346, filed Feb. 15, 2023; and U.S. patent application Ser. No. 18/110,348, filed Feb. 15, 2023. BACKGROUND An integrated circuit (“IC”) is a device that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often defined on a semiconductor substrate and interconnected with metal wiring and vias to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC typically includes multiple layers of wiring and vias that interconnect its electronic and circuit components. SUMMARY Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction. Also, the first and second wiring layers in some embodiments belong to the first set, while in other embodiments the first and second wiring layers belong to the second set. Each preferred wiring direction in some embodiments is a Manhattan direction (i.e., a horizontal direction or a vertical direction), with the preferred wiring directions of different adjacent layers alternating between horizontal and vertical directions. The preferred wiring directions in other embodiments include other wiring directions (e.g., 45 or 60 degree wiring directions), with successive neighboring layers having different preferred wiring directions. In some embodiments, the preferred wiring direction on each layer is the direction that includes at least a certain threshold amount (e.g., 90% or 95%) of the wiring on that layer. In some embodiments, the non-preferred direction wiring on each layer of the first set of wiring layers includes interconnect wiring (also called wiring connection) that traverses in more than eight directions. In some embodiments, each layer of the first set of wiring layers includes rectilinear wires (i.e., wires with only straight segments) and curvilinear wires (i.e., wires with at least one curved segment). In some embodiments, the first set of wiring layers of the IC is used for wire connections that are shorter than the wire connections defined on the second set of wiring layers. In some embodiments, the first set of wiring layers in some embodiments is used for short local connections, while the second set of wiring layers is used for longer connections. The electronic design automation (EDA) tools (e.g., the router and compactor) that define the design of the IC in some embodiments account for the preferred and non-preferred directions on each wiring layer while defining the routes that result in the metal wiring on these layers. In some embodiments, when the first set of wiring layers includes the third wiring layer and/or the fourth wiring layer, the EDA tools define NPD curvilinear routes for the third and/or fourth wiring layers, but also define NPD curvilinear routes for the first and second wiring layers. However, in some of these embodiments, the first and second wiring layers have preferred direction wiring in some of their regions, such as the regions that are used for connections that are needed to form the electronic components (e.g., the transistors) and circuit blocks (e.g., IP blocks) that are defined on the IC's substrate at locations below these regions. In some embodiments, the EDA tools use the unused spaces on the first and second wiring layers to define NPD rectilinear and/or curvilinear routes, which result in NPD rectilinear/curvilinear wiring on the corresponding layers of the manufactured IC. The NPD rectilinear/curvilinear wiring on the first and second layers augments the NPD rectilinear/curvilinear wiring on the third and/or f