US-12626047-B2 - Computing and displaying a predicted overlap shape in an IC design based on predicted misalignment of metal layers

Abstract

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Inventors

• Donald Oriordan
• Akira Fujimura
• George Janac

Assignees

• D2S, INC.

Dates

Publication Date

20260512

Application Date

20221122

Claims (18)

1. 1 . An electronic design automation (EDA) method for producing a predicted overlap shape of a multi-layer interface of an integrated circuit (IC) design, the method comprising: generating the IC design with at least two defined shapes for the multi-layer interface on at least two layers of the IC design; receiving from a designer data that specifies how to model misalignment between the two layers; using the received data to misalign the two IC-design layers and thereby misalign the two defined shapes of the multi-layer interface; generating the predicted overlap shape of the multi-layer interface from the misaligned two defined shapes; and presenting the predicted overlap shape for display on a display screen, wherein receiving the data comprises providing a set of tools in a graphical user interface (GUI) to allow the designer to provide data that specifies how to model misalignment between the two layers, the set of UI tools providing to the designer a representative selection of misalignment translation values to misalign the two layers.
2. 2 . The EDA method of claim 1 , wherein the two defined shapes are a first pair of later-defined shapes that predict how a second pair of earlier-defined shapes for the multi-layer interface would appear after a subsequent manufacturing stage.
3. 3 . The EDA method of claim 2 further comprising using a machine-trained network to produce at least the first pair of later-defined shapes from the second pair of earlier-defined shapes, the machine-trained network producing a predicted first pair of shapes by accounting for deformities produced during the subsequent manufacturing stage.
4. 4 . The EDA method of claim 3 , wherein the machine-trained network further accounts for a variation in a manufacturing process associated with the subsequent manufacturing stage.
5. 5 . The EDA method of claim 1 , wherein the predicted overlap shape is presented to allow the designer to assess feasibility of manufacturing the IC based on the design.
6. 6 . The EDA method of claim 1 , wherein the representative selection uses vector directions commensurate with a plurality of compass directions, and a user specified maximum misalignment value.
7. 7 . The EDA method of claim 6 , wherein the plurality of compass directions are 4 cardinal compass directions.
8. 8 . The EDA method of claim 6 , wherein the plurality of compass directions are 4 ordinal compass directions.
9. 9 . The EDA method of claim 6 , wherein the plurality of compass directions are 4 cardinal and 4 ordinal compass directions.
10. 10 . A non-transitory machine readable medium storing an electronic design automation (EDA) program for producing a predicted overlap shape of a multi-layer interface of an integrated circuit (IC) design, the program for execution by at least one processing unit of a computer, the program comprising sets of instructions for: generating the IC design with at least two defined shapes for the multi-layer interface on at least two layers of the IC design; receiving from a designer data that specifies how to model misalignment between the two layers; using the received data to misalign the two IC-design layers and thereby misalign the two defined shapes of the multi-layer interface; generating the predicted overlap shape of the multi-layer interface from the misaligned two defined shapes; and presenting the predicted overlap shape for display on a display screen, wherein receiving the data comprises providing a set of tools in a graphical user interface (GUI) to allow the designer to provide data that specifies how to model misalignment between the two layers, the set of UI tools providing to the designer a representative selection of misalignment translation values to misalign the two layers.
11. 11 . The non-transitory machine readable medium of claim 10 , wherein the two defined shapes are a first pair of later-defined shapes that predict how a second pair of earlier-defined shapes for the multi-layer interface would appear after a subsequent manufacturing stage.
12. 12 . The non-transitory machine readable medium of claim 11 , wherein the program further comprises a set of instructions for using a machine-trained network to produce at least the first pair of later-defined shapes from the second pair of earlier-defined shapes, the machine-trained network producing a predicted first pair of shapes by accounting for deformities produced during the subsequent manufacturing stage.
13. 13 . The non-transitory machine readable medium of claim 12 , wherein the machine-trained network further accounts for a variation in a manufacturing process associated with the subsequent manufacturing stage.
14. 14 . The non-transitory machine readable medium of claim 10 , wherein the predicted overlap shape is presented to allow the designer to assess feasibility of manufacturing the IC based on the design.
15. 15 . The non-transitory machine readable medium of claim 10 , wherein the representative selection uses vector directions commensurate with a plurality compass directions, and a user specified maximum misalignment value.
16. 16 . The non-transitory machine readable medium of claim 10 , wherein the representative selection uses a user-specified maximum misalignment value as a magnitude of the translation values.
17. 17 . The non-transitory machine readable medium of claim 10 , wherein the set of instructions for presenting for display comprises a set of instructions for generating the display by superimposing the predicted overlap shape on the design layout.
18. 18 . The non-transitory machine readable medium of claim 10 , wherein the set of instructions for generating the predicted overlap shape comprises sets of instructions for: for the multi-layer interface: identifying one shape on each layer of at least two layers traversed by the multi-layer interface; and intersecting the identified shapes to produce a predicted minimum overlap shape for the multi-layer interface.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application is related to the following applications having a similar specification and figures: U.S. patent application Ser. No. 17/992,897, filed Nov. 22, 2022; U.S. patent application Ser. No. 17/992,906, filed Nov. 22, 2022; and U.S. patent application Ser. No. 17/992,907, filed Nov. 22, 2022. BACKGROUND Some of the biggest challenges in chip scaling involve contacts and interconnects. Since interconnects become more compact at each process node, this has an adverse effect on RC (resistance-capacitance) delay (and hence timing, max operating frequency, etc.) in integrated circuit (IC) designs. Transistor devices have traditionally scaled well, e.g., with the translation from planar to fin field-effect transistor (FinFET) devices. However, the contacts and interconnects have shrunk as the devices have shrunk, which leads to significant increase in resistance. FIG. 1 illustrates an example of an interconnect 102, a contact 104 and a transistor 106 at various nodes. Transistor devices (Front-End-of-LINE FEOL devices) and IC interconnects Back End Of Line (BEOL) are connected by a contact layer called the middle-of-line (MOL), in which contacts are formed. Contacts are three-dimensional structures with a small gap, which is typically filled with a conductive material, such as tungsten. The tungsten structure, called a tungsten plug, is sandwiched between a liner material (titanium) and a barrier layer (titanium nitride). The entire structure is called a contact. At 16 nm/14 nm process nodes, the volume of the tungsten conductor material is relatively small. Hence, an electrical signal flows through the relatively smaller amount of conductive metal, causing a significant increase in contact resistance. The electrical resistance of an object is a measure of its opposition to the flow of electric current and so relates to the difficulty to pass a current through a conductor (such as a contact). Contact resistance has become more problematic at each process node. Interconnects are structures that connect two or more circuit elements (such as transistors) together electrically. Modern integrated circuits at the leading edge process geometries now have in the range of 9 to 12 metal (copper) layers, if not more. Each layer contains a number of wire structures, and wires on different layers are electrically connected with vias. FIG. 2 illustrates several examples of interconnect layers 200. Copper interconnects in IC designs are commonly fabricated using a dual damascene process in which a low-k dielectric material is deposited on the surface of the device. The low-k dielectric material insulates one device layer from another. After this, the vias and trenches are patterned and the resulting structure is etched, forming a via and trench. FIG. 3 illustrates an example of a dual-damascene fabrication process 300 with the etched via 302 and trench 304. FIG. 4 illustrates an example of interconnect line widths 400 that have had to scale in size as transistor sizes have shrunk in modern processes. This has led to substantially increased resistance value (towards the left side of the graph in the figure). Over the last decade or more, interconnect dimensions have continued to scale along with the transistor devices, leading to an increase in overall wire length (a multi-fold increase since the 90 nm node) coupled with increases in resistance and capacitance from increasingly closely spaced, thin wires. Foundries have been able to reduce the contribution to RC delay from resistance by increasing the aspect ratio (effectively, the height) of the interconnect (with a resulting increase in coupling capacitance), but resistance has become an increasingly difficult problem to solve. FIG. 5 illustrates an example of BEOL performance/area/cross scaling being the foremost issue for 10 nm/7 nm process nodes and the difficulty at various process nodes. Smaller process nodes are represented to the right, and the y-axis is drawn on a log scale. FIG. 5 illustrates how the interconnect RC delay has increased by multiple orders of magnitude, even as the transistor delay has decreased by less than a single order of magnitude, from 90 nm process down to 7 nm processes. A large portion of the RC delay can be attributed to via resistances, and via resistances significantly increase as wire widths decrease. FIG. 6 illustrates an example of a relationship between via resistance for both standard and chamfered vias, as a function of the critical dimension for a metal layer. A key goal in IC manufacturing is to align the various layers of a wafer in a precise manner, which represents good overlay. For example, a transistor gate on one layer needs to be connected through a contact in another layer and to an interconnect wire in another layer. They all have to be lined up on top of each other. Since such alignment is not perfect in true manufacturing processes, there is tolerance built into the