US-12626073-B2 - High-speed pulse-width modulator

Abstract

Input digital bits are split into a first part and a second part. Digital-to-analog converter (DAC) is configured to encode the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units, where the fraction is equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part. Crossbar array coupled with the DAC stores weights encoded as analog conductance on resistive memory devices, and is configured to generate analog computation output responsive to the analog form of the input digital bits applied to the crossbar array. Analog-to-digital converter (ADC) coupled with the crossbar array, is configured to digitize the analog computation output from the crossbar array.

Inventors

• Abhairaj Singh
• Kumudu Geethan Karunaratne
• Manuel Le Gallo-Bourdeau
• Abu Sebastian

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20240522

Claims (20)

1. 1 . A device comprising: a processor configured to split input digital bits into a first part and a second part; a digital-to-analog converter (DAC) coupled with the processor, and configured to encode the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units, the fraction being equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part; a crossbar array coupled with the DAC, and structured with resistive memory devices, the crossbar array configured to store weights, wherein each of the weights is encoded as analog conductance using at least one of the resistive memory devices, the crossbar array configured to generate analog computation output responsive to the analog form of the input digital bits applied to the crossbar array; and an analog-to-digital converter (ADC) coupled with the crossbar array, and configured to digitize the analog computation output from the crossbar array.
2. 2 . The device of claim 1 , wherein the time unit is a clock cycle time of a clock used on the device.
3. 3 . The device of claim 1 , wherein the time unit is a nanosecond and clock speed of a clock used on the device is 1 gigahertz (GHz).
4. 4 . The device of claim 1 , wherein number of bits for the first part into which the input digital bits are split is configurable.
5. 5 . The device of claim 1 , wherein number of bits for the second part into which the input digital bits are split is configurable.
6. 6 . The device of claim 1 , wherein a speedup factor that increases speed at which the crossbar array performs computation is proportional to the number of bits in the second part.
7. 7 . The device of claim 1 , wherein the DAC includes a delay chain coupled with a multiplexer that is configured to select the delay based on the magnitude of the second part, the DAC further configured to trigger a local delay clock responsive to the multiplexer selecting the delay based on the magnitude of the second part.
8. 8 . The device of claim 1 , wherein the activation pulse is a voltage pulse.
9. 9 . The device of claim 1 , wherein the ADC is configured to multiply output from the crossbar array by a speed factor that is equivalent to two raised to power of number of bits in the second part.
10. 10 . The device of claim 1 , wherein the analog computation output is an analog matrix-vector-multiplication output.
11. 11 . A method comprising: splitting input digital bits into a first part and a second part; encoding, by a digital-to-analog converter (DAC), the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units, the fraction being equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part; generating, by a crossbar array storing weights as analog conductance on resistive memory devices, analog computation output, responsive to the analog form of the input digital bits applied to the crossbar array; and digitizing, by an analog-to-digital converter (ADC), the analog computation output from the crossbar array.
12. 12 . The method of claim 11 , wherein the time unit is a clock cycle time of a clock used on the device.
13. 13 . The method of claim 11 , wherein the time unit is a nanosecond and clock speed of a clock used on the device is 1 gigahertz (GHz).
14. 14 . The method of claim 11 , wherein number of bits for the first part into which the input digital bits are split is configurable.
15. 15 . The method of claim 11 , wherein number of bits for the second part into which the input digital bits are split is configurable.
16. 16 . The method of claim 11 , wherein a speedup factor that increases speed at which the crossbar array performs computation is proportional to the number of bits in the second part.
17. 17 . The method of claim 11 , wherein the encoding includes using a delay chain coupled with a multiplexer and triggering a local delay clock responsive to the multiplexer selecting the delay based on the magnitude of the second part.
18. 18 . The method of claim 11 , wherein the activation pulse is a voltage pulse.
19. 19 . The method of claim 11 , wherein the digitizing includes multiplying the analog computation output from the crossbar array by a speed factor that is equivalent to two raised to power of number of bits in the second part.
20. 20 . The method of claim 11 , wherein the analog computation output is an analog matrix-vector-multiplication output.

Description

BACKGROUND The present application relates generally to computers and computer applications, and more particularly to pulse-width modulators. Such pulse-width modulators can be used in performing in-memory matrix multiplications. BRIEF SUMMARY The summary of the disclosure is given to aid understanding of a computer system and method of high-speed pulse-width modulator, e.g., to perform in-memory matrix multiplication, and not with an intent to limit the disclosure or the invention. It should be understood that various aspects and features of the disclosure may advantageously be used separately in some instances, or in combination with other aspects and features of the disclosure in other instances. Accordingly, variations and modifications may be made to the computer system and/or their method of operation to achieve different effects. In some embodiments, a device includes a processor configured to split input digital bits into a first part and a second part. The device also include a digital-to-analog converter (DAC) coupled with the processor. The DAC is configured to encode the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units. The fraction is equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part. The device also includes a crossbar array coupled with the DAC. The crossbar array is structured with resistive memory devices. The crossbar array is also configured to store weights, where each of the weights is encoded as analog conductance using at least one of the resistive memory devices. The crossbar array is also configured to generate analog computation output responsive to the analog form of the input digital bits applied to the crossbar array. The device also includes an analog-to-digital converter (ADC) coupled with the crossbar array. The ADC is configured to digitize the analog computation output from the crossbar array. In some embodiments, a method includes splitting input digital bits into a first part and a second part. The method also include encoding, by a digital-to-analog converter (DAC), the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units. The fraction is equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part. The method also includes generating, by a crossbar array storing weights as analog conductance on resistive memory devices, analog computation output, responsive to the analog form of the input digital bits applied to the crossbar array. The method also includes digitizing, by an analog-to-digital converter (ADC), the analog computation output from the crossbar array. Further features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a device that performs analog matrix-vector multiplication (MVM) in some embodiments. FIG. 2 illustrates a digital-to-analog converter in some embodiments. FIG. 3 illustrates an analog to digital converter in some embodiments. FIG. 4 is a block diagram illustrating a process flow in components of a device or system in some embodiments. FIG. 5 illustrates an example of pre-encoding an input, where the input bits are divided into two parts in some embodiments for encoding by a digital-to-analog converter (DAC) operating in bit-parallel mode. FIG. 6 illustrates a digital-to-analog converter (DAC) in some embodiments. FIG. 7 is a diagram illustrating components of a circuit that implements a digital-to-analog converter (DAC) in some embodiments. FIG. 8 shows a corresponding timing diagram of various components of a circuit shown in FIG. 7 in some embodiments. FIG. 9 illustrates examples of speedup factors, implemented based on number of input bits divided into integral and fractional parts, in some embodiments. FIG. 10 is a block diagram illustrating a process flow and device components that perform analog MVM (AMVM) in some embodiments. FIG. 11 is a block diagram illustrating a current controlled oscillator (CCO)-based analog-to-digital converter (ADC) in some embodiments. FIG. 12 is a flow diagram illustrating a method of performing computation using a crossbar array of resistive memory devices in some embodiments. DETAILED DESCRIPTION FIG. 1 illustrates an example of a device that performs analog matrix-vector multiplication (MVM) in some embodiments. Such a device can be used in neural network implementations, such as for deep neural network implementations, where