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US-12626115-B2 - Processing device and electronic device having the same

US12626115B2US 12626115 B2US12626115 B2US 12626115B2US-12626115-B2

Abstract

A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

Inventors

  • Seungchul Jung
  • SangJoon Kim
  • Sungmeen Myung

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260512
Application Date
20210308
Priority Date
20200720

Claims (20)

  1. 1 . A processing device comprising: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells comprises a via penetrating through the variable resistor layer and directly connecting at least one of the switches of the at least one of the plurality of bitcells to at least one of the active variable resistors of another one of the plurality of bitcells.
  2. 2 . The processing device of claim 1 , wherein configurations of the via, the active variable resistors, and the inactive variable resistors of adjacent bitcells among the at least one of the plurality of bitcells are symmetrical with each other about a boundary between the adjacent bitcells.
  3. 3 . The processing device of claim 1 , wherein each of the plurality of bitcells respectively comprises the via.
  4. 4 . The processing device of claim 1 , wherein the plurality of bitcells comprise serially connected bitcells, and the serially connected bitcells comprise one via for every two adjacent bitcells.
  5. 5 . The processing device of claim 1 , wherein the plurality of bitcells comprise 64 or more serially connected bitcells.
  6. 6 . The processing device of claim 1 , wherein the plurality of bitcells form a bitcell array including 64 or more bitcell lines, and each of the bitcell lines comprises serially connected bitcells from among the plurality of bitcells.
  7. 7 . The processing device of claim 1 , wherein at least one of the switches of each of the plurality of bitcells comprises a common source and two electrically connected drains.
  8. 8 . The processing device of claim 1 , wherein the processing device is an in-memory processing unit.
  9. 9 . An electronic device comprising: the processing device of claim 1 , wherein the processing device is a neural network device; and a processor configured to control a function of the neural network device.
  10. 10 . A processing device comprising: a bitcell including: a variable resistor layer including a plurality of active variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein the variable resistor layer comprises at least one via penetrating through the variable resistor layer and directly connecting at least one of the switches of the bitcell to at least one active variable resistor of another bitcell.
  11. 11 . The processing device of claim 10 , wherein the metal layers comprise a metal layer stacked on the variable resistor layer and including a wire connecting an upper end portion of the via to an upper end portion of at least one of the active variable resistors.
  12. 12 . The processing device of claim 11 , wherein the variable resistor layer further comprises inactive variable resistors not electrically connected to the switches, and a minimum distance between the at least one via and the active variable resistors is greater than a minimum distance between the at least one via and the inactive variable resistors.
  13. 13 . The processing device of claim 12 , wherein the variable resistor layer comprises a plurality of vias, and a minimum distance between vias is less than the minimum distance between the at least one via and the inactive variable resistors.
  14. 14 . The processing device of claim 12 , wherein the minimum distance between the at least one via and the inactive variable resistors is greater than both a minimum distance between the inactive variable resistors and a minimum distance between the inactive variable resistors and the active variable resistors.
  15. 15 . The processing device of claim 12 , wherein the variable resistor layer comprises a plurality of vias, and a minimum distance between the vias is substantially within 0.10 μm to 0.40 μm.
  16. 16 . The processing device of claim 12 , wherein the minimum distance between the at least one via and the active variable resistors is substantially within 0.50 μm to 1.20 μm.
  17. 17 . The processing device of claim 12 , wherein the minimum distance between the at least one via and the inactive variable resistors is substantially within 0.30 μm to 0.60 μm.
  18. 18 . The processing device of claim 10 , wherein each of the active variable resistors is a magnetic tunnel junction (MTJ) device.
  19. 19 . An electronic device comprising: the processing device of claim 10 , wherein the processing device is a neural network device; and a processor configured to control a function of the neural network device.
  20. 20 . An electronic device comprising: a neural network device; and a processor configured to control a function of the neural network device, wherein the neural network device comprises a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied to ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, and wherein at least one of the plurality of bitcells comprises a via penetrating through the variable resistor layer and directly connecting at least one of the switches of the at least one of the plurality of bitcells to at least one of the active variable resistors of another one of the plurality of bitcells.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit under 35 U.S.C. § 119(a) of Korean Patent Application No. 10-2020-0089853, filed on Jul. 20, 2020, and Korean Patent Application No. 10-2021-0002215, filed on Jan. 7, 2021, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference for all purposes. BACKGROUND 1. Field The following description relates to a processing device and an electronic device having the processing device. 2. Description of the Related Art Neural network devices may perform a multiply-accumulate (MAC) operation of repeating multiplications and additions. A neural network may repeatedly perform a MAC operation of multiplying the values of nodes of a previous layer with weights mapped to the nodes and adding multiplication results at a specific node, and may perform an operation of applying an activation function to a result of the MAC operation. To this end, a memory access operation of loading an appropriate input and weight at a desired or determined time point may also be performed. However, such neural network operations, such as the MAC operation, may not be efficiently performed using other hardware architecture instead of a generally known digital computer. SUMMARY This Summary is provided to introduce a selection of concepts in simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In one general aspect, a processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors. Configurations of the via, the active variable resistors, and the inactive variable resistors of adjacent bitcells among the at least one of the bitcells may be symmetrical with each other about a boundary between the adjacent bitcells. Each of the plurality of bitcells respectively may include the via. The plurality of bitcells may include serially connected bitcells, and the serially connected bitcells may include one via for every two adjacent bitcells. The plurality of bitcells may include 64 or more serially connected bitcells. The plurality of bitcells may form a bitcell array including 64 or more bitcell lines, and each of the bitcell lines may include serially connected bitcells from among the bitcells. At least one of the switches of each of the bitcells may include a common source and two electrically connected drains. The processing device may be an in-memory processing unit. An electronic device may include: the processing device, wherein the processing device is a neural network device; and a processor configured to control a function of the neural network device. In another general aspect, a processing device includes: a variable resistor layer including a plurality of active variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein the variable resistor layer may include at least one via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors. The metal layers may include a metal layer stacked on the variable resistor layer and including a wire connecting an upper end portion of the via to an upper end portion of at least one of the active variable resistors. The variable resistor layer further may include inactive variable resistors not electrically connected to the switches, and a minimum distance between the at least one via and the active variable resistors may be greater than a minimum distance between the at least one via and the inactive variable resistors. The variable resistor layer may include a plurality of vias, and a minimum distance between vias may be less than the minimum distance between the at least one via and the inactive variable resistors. The minimum distance between the at least one