US-12626176-B2 - Systems and methods for scalable quantum computing

US12626176B2US 12626176 B2US12626176 B2US 12626176B2US-12626176-B2

Abstract

A superconducting circuit includes four superconducting qubits communicatively coupled by a 4-qubit even-parity stabilizer. The 4 -qubit even-parity stabilizer includes a superconducting stabilizer loop, and four inductances, each inductance inductively communicatively coupled to an inductance of a respective one of the four superconducting qubits. The 4-qubit even-parity stabilizer also includes a parity-enforcing super-conducting qubit communicatively coupled to the superconducting loop. A quantum processor comprises four Josephson parametric amplifiers communicatively coupled by a 4-qubit even-parity stabilizer. The Josephson parametric amplifiers comprise pairs of superconducting microwave resonators communicatively coupled by a compound-compound Josephson junction. The 4-qubit even-parity stabilizer includes a superconducting loop, four inductances inductively communicatively coupled to an inductance of a respective one of the four Josephson parametric amplifier, and a parity-enforcing Josephson parametric amplifier communicatively coupled to the superconducting loop.

Inventors

Richard G. Harris

Assignees

D-WAVE SYSTEMS INC.

Dates

Publication Date: 20260512
Application Date: 20210325

Claims (9)

1 . A quantum processor comprising a first, a second, a third, and a fourth Josephson parametric amplifier, wherein the first, the second, the third, and the fourth parametric amplifiers are communicatively coupled to one another by a 4 -qubit even- parity stabilizer, the 4-qubit even-parity stabilizer comprising: a superconducting loop, the superconducting loop which includes a material that is superconducting at or below a critical temperature, the superconducting loop which includes a crossover; a first, a second, a third, and a fourth inductance of the superconducting loop, each of the first, the second, the third, and the fourth inductance inductively communicatively coupled to an inductance of a respective Josephson parametric amplifier; and a parity-enforcing Josephson parametric amplifier, wherein the parity-enforcing Josephson parametric amplifier is communicatively coupled to the superconducting loop.
2 . The quantum processor of claim 1 , wherein each of the first, the second, the third, and the fourth Josephson parametric amplifiers comprises a respective pair of superconducting microwave resonators, each superconducting microwave resonator of the respective pair of superconducting microwave resonators communicatively coupled to each other by a compound-compound Josephson junction.
3 . The quantum processor of claim 2 , wherein each of the first, the second, the third and the fourth Josephson parametric amplifiers comprises: a respective compound-compound Josephson junction; and a respective first control circuit communicatively coupled to the respective compound-compound Josephson junction of the first, the second, the third and the fourth Josephson parametric amplifiers, wherein each respective first control circuit comprises: an analog direct current (DC current) bias, the analog DC current bias communicatively coupled to the respective compound-compound Josephson junction of the first, the second, the third and the fourth Josephson parametric amplifiers; a digital-to-analog converter (DAC), the DAC communicatively coupled to the respective compound-compound Josephson junction of the first, the second, the third and the fourth Josephson parametric amplifiers; and a respective first microwave drive communicatively coupled to a respective first tunable mutual inductance, wherein the respective first tunable mutual inductance is communicatively coupled to the respective compound-compound Josephson junction of the first, the second, the third and the fourth Josephson parametric amplifiers.
4 . The quantum processor of claim 3 , wherein the respective first tunable mutual inductance of each of the respective first control circuit is inductively communicatively coupled to the respective compound-compound Josephson junction of the first, the second, the third and the fourth Josephson parametric amplifiers and each of the analog DC current bias and each of the DAC of the respective first control circuit are inductively communicatively coupled to the respective compound-compound Josephson junction of the first, the second, the third and the fourth Josephson parametric amplifiers.
5 . The quantum processor of claim 3 , wherein each respective first control circuit is operable to control strengths of X-terms and Z-terms of an effective Hamiltonian via a resonant drive at a first angular frequency, and via a parametric drive at a second angular frequency, the second angular frequency equal to a difference between twice the first angular frequency and a time-dependent de-tuning frequency.
6 . The quantum processor of claim 3 , wherein each of the first, the second, the third and the fourth Josephson parametric amplifiers further comprises a respective second control circuit, each respective second control circuit comprising a respective second microwave drive communicatively coupled to a respective second tunable mutual inductance, wherein each respective second tunable mutual inductance is communicatively coupled to the respective compound-compound Josephson junction of the first, the second, the third and the fourth Josephson parametric amplifiers.
7 . The quantum processor of claim 6 , wherein each respective second tunable mutual inductance of the respective second control circuit is inductively communicatively coupled to the respective compound-compound Josephson junction of the first, the second, the third and the fourth Josephson parametric amplifiers.
8 . The quantum processor of claim 6 , wherein each respective first and second tunable mutual inductance comprises a superconducting loop interrupted by a compound Josephson junction.
9 . The quantum processor of claim 2 , wherein each of the superconducting microwave resonators in the respective pair of superconducting resonators of the first, the second, the third, and the fourth Josephson parametric amplifiers is one of: a coaxial transmission line resonator, and a ladder circuit comprising a plurality of inductor-capacitor (LC) circuits electrically communicatively coupled in series with one another.

Description

FIELD This disclosure generally relates to systems and methods for scalable quantum computing, and, in particular, circuits for providing control and communicative coupling between devices. BACKGROUND Superconducting Processor A computer processor may take the form of an analog processor, for instance a quantum processor such as a superconducting quantum processor. A superconducting quantum processor may include a number of qubits and associated local bias devices, for instance two or more superconducting qubits. Further detail and embodiments of exemplary quantum processors that may be used in conjunction with the present systems, methods, and apparatus are described in U.S. Pat. Nos. 7,533,068, 8,195,596, 8,190,548, and PCT Patent Application Serial No. PCT/US2009/037984. A superconducting processor may be a processor that is not intended for quantum computing, and operates, for example, by principles that govern the operation of classical computer processors. A computing system may in general include a quantum processor and/or a classical processor. A computing system may be a hybrid system that includes a quantum processor and a classical processor. In some implementations, at least one of the quantum processor and the classical processor is a superconducting processor. Superconducting Qubits A superconducting quantum processor may include superconducting qubits. Superconducting qubits may be formed in a superconducting integrated circuit from superconducting material (e.g., aluminum and/or niobium). Superconducting qubits may be categorized by a physical property used to encode information in the qubits. For example, superconducting qubits may be categorized into charge, flux, and phase qubits. Charge qubits can store and manipulate information in charge states of the qubit. Flux qubits can store and manipulate information in a variable related to a magnetic flux through a portion of the qubit. Phase qubits can store and manipulate information in a variable related to a difference in a superconducting phase between two regions of the qubit. Hybrid devices can use two or more of charge, flux and phase degrees of freedom. Superconducting qubits commonly include at least one Josephson junction. A Josephson junction is a small interruption in an otherwise continuous superconducting current path and is typically realized by a thin insulating barrier sandwiched between two superconducting electrodes. A Josephson junction can be formed as a three-layer or “trilayer” structure. Superconducting qubits are further described in, for example, U.S. Pat. Nos. 7,876,248, 8,035,540, and 8,098,179. Some implementations of superconducting flux qubits include a superconducting loop (also referred to in the present application as a qubit loop) that is interrupted by at least one Josephson junction. Some implementations include multiple superconducting loops connected in series and/or in parallel with one another. Some implementations include multiple Josephson junctions connected either in series or in parallel with one another. A pair of Josephson junctions that are connected in parallel with each another is referred to as a compound Josephson junction (CJJ). It is understood that the behavior of a CJJ may be modeled as a single effective Josephson junction, similar to the way in which the behavior of multiple resistors connected in parallel with one another may be modeled as a single effective resistance. A compound Josephson junction in which at least one of the constituent Josephson junctions is itself a compound Josephson junction is referred to in the present application as a compound-compound Josephson junction (CCJJ). Hamiltonian Description of a Quantum Processor In accordance with some implementations of the present systems and devices, a quantum processor may be designed to perform adiabatic quantum computation and/or quantum annealing. A common problem Hamiltonian includes a first component proportional to diagonal single-qubit terms and a second component proportional to diagonal multi-qubit terms, and may be expressed, for example, as follows: Hp∝-ε2[∑i=1Nhi⁢σiz+∑j>iNJi⁢j⁢σiz⁢σjz] where N represents the number of qubits, σiz is a Pauli z-matrix for the ith qubit, hi and Jij are dimensionless local fields for the qubits and couplings between qubits, respectively, and E is a characteristic energy scale for Hp. The term σiz is an example of a diagonal single-qubit term, and the term σizσjz is an example of a diagonal two-qubit term. A Hamiltonian may be physically realized by an implementation of superconducting qubits, for example. The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings. BRIEF SUMMARY A superconducting circuit may be summarized as comprising a Josephson parametric amplifier, th