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US-12626185-B2 - Signal combiner

US12626185B2US 12626185 B2US12626185 B2US 12626185B2US-12626185-B2

Abstract

In certain aspects, a receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.

Inventors

  • Lai Kan Leung
  • Xinmin Yu
  • Chirag Dipak Patel
  • Rajagopalan Rangarajan

Assignees

  • QUALCOMM INCORPORATED

Dates

Publication Date
20260512
Application Date
20220318

Claims (20)

  1. 1 . A combiner, comprising: first amplifiers, wherein each one of the first amplifiers comprises an input and an output; second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are directly connected to a node; transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers; a load coupled to the node; and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.
  2. 2 . The combiner of claim 1 , wherein the load is directly connected to the node.
  3. 3 . The combiner of claim 2 , wherein the load comprises an inductor or a transformer.
  4. 4 . The combiner of claim 1 , wherein each one of the second amplifiers is configured as a buffer amplifier.
  5. 5 . The combiner of claim 1 , wherein each one of the second amplifiers has approximately unity gain.
  6. 6 . The combiner of claim 1 , wherein each one of the second amplifiers is a common gate amplifier.
  7. 7 . The combiner of claim 1 , wherein each one of the receiver elements comprises a phase shifter configured to receive a signal from a respective antenna and shift a phase of the signal from the respective antenna by a respective phase shift to generate a phase-shifted signal, or wherein each one of the receiver elements comprises a phase shifter configured to receive a local oscillator signal and shift a phase of the local oscillator signal by a respective phase shift to generate a respective phase-shifted local oscillator signal.
  8. 8 . The combiner of claim 7 , wherein each one of the receiver elements comprises a mixer configured to receive the phase-shifted signal or the phase-shifted local oscillator signal.
  9. 9 . The combiner of claim 1 , wherein each one of the first amplifiers is a current amplifier.
  10. 10 . The combiner of claim 1 , wherein each one of the first amplifiers is a transconductance amplifier.
  11. 11 . The combiner of claim 1 , wherein each one of the second amplifiers has an electronically adjustable channel width.
  12. 12 . The combiner of claim 1 , wherein a first one of the first amplifiers is integrated on a chip, a first one of the second amplifiers is integrated on the chip, a first one of the transmission lines is integrated on the chip, and the first one of the transmission lines is coupled between the output of the first one of the first amplifiers and the input of the first one of the second amplifiers.
  13. 13 . The combiner of claim 12 , wherein the load is integrated on the chip.
  14. 14 . A combiner, comprising: a plurality of inputs; a plurality of first amplifiers respectively coupled to the plurality of inputs; a plurality of transistors directly connected to a node, wherein each transistor of the plurality of transistors comprises a gate configured to be coupled to a bias voltage; a plurality of transmission lines, wherein each transmission line of the plurality of transmission lines is coupled between a respective first amplifier of the plurality of first amplifiers and a respective transistor of the plurality of transistors; and a load coupled to the node.
  15. 15 . The combiner of claim 14 , wherein the load is directly connected to the node.
  16. 16 . The combiner of claim 15 , wherein the load comprises an inductor or a transformer.
  17. 17 . The combiner of claim 14 , wherein each amplifier of the plurality of first amplifiers is a current amplifier or a transconductance amplifier.
  18. 18 . The combiner of claim 14 , further comprising a plurality of switches, wherein each switch of the plurality of switches is configured to selectively couple the gate of a respective transistor of the plurality of transistors to a respective bias voltage.
  19. 19 . The combiner of claim 14 , further comprising a plurality of switches, wherein each switch of the plurality of switches is coupled between a respective transistor of the plurality of transistors and a respective transmission line of the plurality of transmission lines.
  20. 20 . The combiner of claim 14 , wherein the plurality of inputs are coupled to a phased antenna array.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation of U.S. patent application Ser. No. 16/557,961, entitled “SIGNAL COMBINER,” filed Aug. 30, 2019, now issued as U.S. Pat. No. 11,283,409, and assigned to the assignee hereof and hereby expressly incorporated by reference in its entirety herein. BACKGROUND Field Aspects of the present disclosure relate generally to wireless communications, and more particularly, to signal combiners for use in phased-array receivers. Background Phased antenna arrays are used in wireless communication systems (e.g., fifth generation (5G) communication systems) operating in the millimeter wave (mmWave) band (e.g., tens of gigahertz). A phased antenna array allows a wireless device to transmit and/or receive signals with high directivity for increased range. SUMMARY The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later. A first aspect relates to a receiver. The receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers. A second aspect relates to a method for signal combining. The method includes receiving signals from receiver elements, amplifying the signals from the receiver elements into first amplified signals, and driving transmission lines with the first amplified signals. The method also includes receiving the first amplified signals from the transmission lines, amplifying the first amplified signals from the transmission lines into second amplified signals, and combining the second amplified signals into a combined signal. To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the described implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of steering the receive direction of a phased antenna array using phase shifters according to certain aspects of the present disclosure. FIG. 2 shows an example of a phased antenna array according to certain aspects of the present disclosure. FIG. 3 shows an example of a phased-array receiver according to certain aspects of the present disclosure. FIG. 4 shows another example of a phased-array receiver according to certain aspects of the present disclosure. FIG. 5 shows yet another example of a phased-array receiver according to certain aspects of the present disclosure. FIG. 6 shows an example of a dual-band phased-array receiver according to certain aspects of the present disclosure. FIG. 7 shows an example of a combiner according to certain aspects of the present disclosure. FIG. 8 shows an example in which inputs of the combiner are coupled to respective receiver elements according to certain aspects of the present disclosure. FIG. 9 shows an exemplary implementation of a current amplifier according to certain aspects of the present disclosure. FIG. 10 shows an exemplary implementation of a current amplifier with an adjustable current gain according to certain aspects of the present disclosure. FIG. 11 shows an example of a combiner including current amplifiers according to certain aspects of the present disclosure. FIG. 12 shows an example of a combiner including common gate amplifiers according to certain aspects of the present disclosure. FIG. 13 shows an example of a combiner including common gate amplifiers with adjustable channel widths according to certain aspects of the present disclosure. FIG. 1