US-12626626-B2 - Gate driver circuit and transparent display device including the same

US12626626B2US 12626626 B2US12626626 B2US 12626626B2US-12626626-B2

Abstract

A gate driver circuit capable of preventing multiple outputs of a dummy stage to prevent malfunction thereof due to deterioration of an element, and a display device including the gate driver circuit. The gate driver circuit includes a plurality of stages for driving a plurality of gate lines, wherein the plurality of stages include: an X-th stage configured to output a carry signal and at least one gate signal; and a dummy stage configured to output a dummy carry signal to the X-th stage in response to the carry signal, wherein the dummy stage is configured to reset the dummy stage in response to the dummy carry signal.

Inventors

Binn Kim

Assignees

LG DISPLAY CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20231215
Priority Date: 20221222

Claims (20)

1 . A gate driver circuit comprising: a plurality of stages sequentially arranged for driving a plurality of gate lines, wherein each of the plurality of stages includes: an X-th stage configured to output a carry signal and at least one gate signal, where X is an integer equal to or greater than 2; and a dummy stage configured to output a dummy carry signal to the X-th stage in response to the carry signal, wherein the dummy stage is configured to reset the dummy stage in response to the dummy carry signal, and includes at least one reset transistor having a channel width smaller than a channel width of a reset transistor included in the X-th stage.
2 . The gate driver circuit of claim 1 , wherein the dummy stage includes: a pull-up transistor configured to pull-up an output in response to a Q node; a pull-down transistor configured to pull-down the output in response to a Qb node; and a reset circuit configured to reset the Q node in response to the dummy carry signal.
3 . The gate driver circuit of claim 2 , wherein the reset circuit includes a first transistor and a second transistor connected to and disposed between the Q node and a base voltage line to which a base voltage is applied, and wherein the first transistor and the second transistor are configured to pull down the Q node to the base voltage in response to the dummy carry signal.
4 . The gate driver circuit of claim 3 , wherein the first transistor and the second transistor are connected in series with each other and disposed between and connected to the Q node and the base voltage line.
5 . The gate driver circuit of claim 3 , wherein each of the first transistor and the second transistor has a smaller channel width than a channel width of each of transistors of a reset circuit of the X-th stage.
6 . The gate driver circuit of claim 5 , wherein each of the first transistor and the second transistor has the channel width equal to 0.5 to 0.7 times of the channel width of each of the transistors of the reset circuit of the X-th stage.
7 . The gate driver circuit of claim 2 , wherein the dummy stage further includes: a first set circuit configured to set the Q node to a power voltage in response to the carry signal; and a second set circuit configured to set the Qb node to a base voltage in response to the carry signal.
8 . The gate driver circuit of claim 7 , wherein the first set circuit includes a third transistor and a fourth transistor connected to and disposed between a power voltage line to which the power voltage is applied and the Q node, and wherein the third transistor and the fourth transistor are configured to pull up the Q node to the power voltage in response to the carry signal.
9 . The gate driver circuit of claim 8 , wherein the third transistor and the fourth transistor are connected in series with each other and disposed between and connected to the power voltage line and the Q node.
10 . The gate driver circuit of claim 7 , wherein the second set circuit includes a fifth transistor connected to and disposed between a base voltage line to which the base voltage is applied and the Qb node, and wherein the fifth transistor is configured to pull down the Qb node to the base voltage.
11 . The gate driver circuit of claim 10 , wherein the fifth transistor is configured to set the Qb node to the base voltage in response to the carry signal.
12 . The gate driver circuit of claim 2 , wherein the pull-up transistor has a source electrode connected to a clock line to which a carry clock signal is applied, wherein the pull-down transistor has a source electrode connected to a base voltage line to which a base voltage is applied.
13 . A gate driver circuit comprising: a plurality of stages sequentially arranged for driving a plurality of gate lines, wherein each of the plurality of stages includes: a (X−1)-th stage configured to output a (X−1)-th carry signal and at least one (X−1)-th gate signal, where X is an integer equal to or greater than 2; an X-th stage configured to output an X-th carry signal and at least one X-th gate signal; a first dummy stage configured to output a first dummy carry signal to the (X−1)-th stage in response to the (X−1)-th carry signal, and to reset the first dummy stage in response to the first dummy carry signal, the first dummy stage including at least one reset transistor having a channel width smaller than a channel width of a reset transistor included in the (X−1)-th stage; and a second dummy stage configured to output a second dummy carry signal to the X-th stage in response to the X-th carry signal and to reset the second dummy stage in response to the second dummy carry signal, the second dummy stage including at least one reset transistor having a channel width smaller than a channel width of a reset transistor included in the X-th stage.
14 . The gate driver circuit of claim 13 , wherein each of the first dummy stage and the second dummy stage includes: a pull-up transistor configured to pull-up an output in response to a Q node; a pull-down transistor configured to pull-down the output in response to a Qb node; and a reset circuit configured to reset the Q node in response to the first dummy carry signal or the second dummy carry signal.
15 . The gate driver circuit of claim 14 , wherein the reset circuit includes a first transistor and a second transistor connected to and disposed between the Q node and a base voltage line to which a base voltage is applied, wherein the first transistor and the second transistor are configured to pull down the Q node to the base voltage in response to the first dummy carry signal or the second dummy carry signal.
16 . The gate driver circuit of claim 15 , wherein each of the first transistor and the second transistor has a smaller channel width than a channel width of each of transistors of a reset circuit of each of the (X−1)-th stage and the X-th stage.
17 . The gate driver circuit of claim 16 , wherein each of the first transistor and the second transistor has the channel width equal to 0.5 to 0.7 times of the channel width of each of the transistors of the reset circuit of each of the (X−1)-th stage and the X-th stage.
18 . The gate driver circuit of claim 14 , wherein each of the first dummy stage and the second dummy stage includes: a first set circuit configured to set the Q node to a power voltage in response to the (X−1)-th carry signal or the X-th carry signal; and a second set circuit configured to set the Qb node to a base voltage in response to the (X−1)-th carry signal or the X-th carry signal.
19 . The gate driver circuit of claim 18 , wherein the first set circuit includes a third transistor and a fourth transistor connected to and disposed between a power voltage line to which the power voltage is applied and the Q node, wherein the third transistor and the fourth transistor are configured to pull up the Q node to the power voltage in response to the (X−1)-th carry signal or the X-th carry signal, and wherein the second set circuit includes a fifth transistor connected to and disposed between a base voltage line to which the base voltage is applied and the Qb node, wherein the fifth transistor is configured to pull down the Qb node to the base voltage in response to the (X−1)-th carry signal or the X-th carry signal.
20 . A transparent display device comprising: a cuttable transparent display panel; and a gate driver circuit configured to drive gate lines of the display panel, wherein the gate driver circuit includes the gate driver circuit according to claim 1 .

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority of Korean Patent Application No. 10-2022-0181500 filed on Dec. 22, 2022, which is hereby incorporated by reference in its entirety. BACKGROUND Field of the Disclosure The present disclosure relates to a display device, and more particularly, to a gate driver circuit, and a transparent display device including the gate driver circuit. Description of the Background As the information society develops, the demand for display devices to display images is increasing in various forms. Thus, various display devices such as liquid crystal display devices and organic light-emitting display devices are being utilized. The display device includes a data driver circuit that supplies data signals to data lines of a display panel and a gate driver circuit that sequentially supplies gate signals to gate lines of a display panel. Recently, as the display device is increasingly thinner, a scheme to embed the gate driver circuit together with a pixel array into a display panel is being developed. The gate driver circuit embedded in the display panels is referred to as a GIP (Gate In Panel) driver circuit. SUMMARY The gate driver circuit is composed of a shift register having a plurality of stages to sequentially output a gate signal. A transparent display panel may be cuttable. When the transparent display panel is cut, the gate driver circuit built into the panel is also cut. When manufacturing a cuttable panel, last two stages among a plurality of stages serve as dummy stages to reset a previous stage. However, since the dummy stage cannot be reset in cutting of the transparent display panel, multiple outputs may occur in the dummy stage during operation of the gate driver circuit. The multi-output of the dummy stage applies an excessive gate bias to a transistor of a reset circuit of the previous stage, thus causing deterioration of the element, which causes the gate driver circuit to malfunction. Accordingly, the present disclosure is directed to a gate driver circuit and a transparent display device including the same that substantially obviate one or more of problems due to limitations and disadvantages described above. More specifically, the present disclosure is to provide a gate driver circuit capable of preventing the multiple outputs of the dummy stage, and thus preventing malfunction due to deterioration of the element, and provide a transparent display device including the gate driver circuit. The present disclosure is also to provide a gate driver circuit capable of preventing the multiple outputs of the dummy stage to secure stability of the gate driver circuit, and provide a transparent display device including the gate driver circuit. Additional features and advantages of the disclosure will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. The present disclosure is not limited to the above-mentioned features. Other features and advantages according to the present disclosure that are not mentioned may be understood based on following descriptions, and may be more clearly understood based on aspects according to the present disclosure. Further, it will be easily understood that the advantages according to the present disclosure may be realized using means shown in the claims or combinations thereof. To achieve these and other advantages and in accordance with the present disclosure, as embodied and broadly described, a plurality of stages for driving a plurality of gate lines, wherein each of the plurality of stages includes an X-th stage configured to output a carry signal and at least one gate signal; and a dummy stage configured to output a dummy carry signal to the X-th stage in response to the carry signal, wherein the dummy stage is configured to reset the dummy stage in response to the dummy carry signal. In another aspect of the present disclosure, a gate driver circuit includes a (X−1)-th stage configured to output a (X−1)-th carry signal and at least one (X−1)-th gate signal; an X-th stage configured to output an X-th carry signal and at least one X-th gate signal; a first dummy stage configured to output a first dummy carry signal to the (X−1)-th stage in response to the (X−1)-th carry signal, and to reset the first dummy stage in response to the first dummy carry signal; and a second dummy stage configured to output a second dummy carry signal to the X-th stage in response to the X-th carry signal and to reset the second dummy stage in response to the second dummy carry signal. In a further aspect of the present disclosure, a transparent display device includes a cuttable transparent display panel; and a gate driver circuit configured to