US-12626631-B2 - Pixel circuit and driving method thereof

Abstract

A pixel circuit and a driving method thereof are provided. The pixel circuit includes a capacitor, a reset circuit, a writing circuit, a driving circuit, and a light-emitting diode. The capacitor is coupled to a node. The reset circuit controlled by a reset signal and is configured to reset a voltage at the node based on a reference voltage. The writing circuit is controlled by a writing signal and is configured to write a gray-level voltage into the capacitor. The driving circuit is controlled by a driving signal and is configured to generate a driving current based on the voltage at the node to drive the light-emitting diode. An enabling period of the reset signal partially overlaps with an enabling period of the writing signal, so that the gray-level voltage is written into the capacitor while the reference voltage is applied to the node.

Inventors

• Yen-Wei YEH
• Wei-Li Lin

Assignees

• AUO Corporation

Dates

Publication Date

20260512

Application Date

20241203

Priority Date

20241025

Claims (14)

1. 1 . A pixel circuit, comprising: a capacitor coupled to a node; a reset circuit controlled by at least one reset signal and configured to reset a voltage at the node based on at least one reference voltage; a writing circuit controlled by a writing signal and configured to write a gray-level voltage into the capacitor and change the voltage at the node to respond to a critical voltage; a driving circuit controlled by a driving signal and configured to generate a driving current based on the voltage at the node; and a light-emitting diode coupled to the driving circuit, wherein brightness of the light-emitting diode changes with the driving current, wherein an enabling period of the at least one reset signal partially overlaps with an enabling period of the writing signal, so that the gray-level voltage is written into the capacitor while the at least one reference voltage is applied to the node, wherein a duration of the enabling period of the writing signal is greater than a duration of an enabling period of the gray-level voltage.
2. 2 . The pixel circuit according to claim 1 , wherein the at least one reference voltage comprises a first reference voltage and a second reference voltage, and the reset circuit comprises: a first transistor, wherein a first terminal thereof is coupled to the first reference voltage, a second terminal thereof is coupled to a first terminal of the capacitor, and a control terminal thereof receives the at least one reset signal; a second transistor, wherein a first terminal thereof is coupled to a second terminal of the capacitor, a second terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the at least one reset signal; and a third transistor, wherein a first terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the at least one reset signal.
3. 3 . The pixel circuit according to claim 2 , wherein the writing circuit comprises: a fourth transistor, wherein a first terminal thereof is coupled to the gray-level voltage, a second terminal thereof is coupled to the first terminal of the capacitor, and a control terminal thereof receives the writing signal; and a fifth transistor, wherein a first terminal thereof is coupled to a third reference voltage, and a control terminal thereof receives the writing signal.
4. 4 . The pixel circuit according to claim 3 , wherein the driving circuit comprises: a sixth transistor, wherein a first terminal thereof is coupled to the light-emitting diode, a second terminal thereof is coupled to the second terminal of the capacitor, and a control terminal thereof receives the driving signal; a seventh transistor, wherein a first terminal thereof is coupled to the second terminal of the capacitor, a second terminal thereof is coupled to the first reference voltage, and a control terminal thereof is coupled to a second terminal of the third transistor and a second terminal of the fifth transistor; and an eighth transistor, wherein a first terminal thereof is coupled to the first terminal of the capacitor, a second terminal thereof is coupled to the control terminal of the seventh transistor, and a control terminal thereof receives the driving signal.
5. 5 . The pixel circuit according to claim 4 , wherein the first transistor to the eighth transistor are P-type transistors, the at least one reset signal is at a logical low level during the enabling period of the at least one reset signal, and the writing signal is at the logical low level during the enable period of the writing signal.
6. 6 . The pixel circuit according to claim 1 , wherein the at least one reference voltage comprises a first reference voltage and a second reference voltage, the at least one reset signal comprises a first reset signal and a second reset signal, and the reset circuit comprises: a first transistor, wherein a first terminal thereof is coupled to the first reference voltage, a second terminal thereof is coupled to a first terminal of the capacitor, and a control terminal thereof receives the first reset signal; a second transistor, wherein a first terminal thereof is coupled to a second terminal of the capacitor, a second terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the second reset signal; and a third transistor, wherein a first terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the first reset signal.
7. 7 . The pixel circuit according to claim 6 , wherein an enabling period of the first reset signal does not overlap with the enabling period of the writing signal, and an enabling period of the second reset signal partially overlaps with the enabling period of the writing signal.
8. 8 . The pixel circuit according to claim 1 , wherein the enabling period of the at least one reset signal ends earlier than the enabling period of the writing signal.
9. 9 . The pixel circuit according to claim 1 , wherein the driving circuit comprises: a first transistor, wherein a first terminal thereof is coupled to a system voltage, and a control terminal thereof receives the driving signal; a second transistor, wherein a first terminal thereof is coupled to a second terminal of the first transistor, a second terminal thereof is coupled to a first terminal of the capacitor, and a control terminal thereof receives the driving signal; a third transistor, wherein a first terminal thereof is coupled to the first terminal of the second transistor, and a control terminal thereof is coupled to a second terminal of the capacitor; and a fourth transistor, wherein a first terminal thereof is coupled to a second terminal of the third transistor, a second terminal thereof is coupled to the light-emitting diode, and a control terminal thereof receives the driving signal.
10. 10 . The pixel circuit according to claim 9 , wherein the at least one reference voltage comprises a first reference voltage and a second reference voltage, and the reset circuit comprises: a fifth transistor, wherein a first terminal thereof is coupled to the second terminal of the capacitor, a second terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the at least one reset signal; and a sixth transistor, wherein a first terminal thereof is coupled to the first terminal of the capacitor, a second terminal thereof is coupled to the first reference voltage, and a control terminal thereof receives the at least one reset signal.
11. 11 . The pixel circuit according to claim 10 , wherein the writing circuit comprises: a seventh transistor, wherein a first terminal thereof is coupled to the first terminal of the capacitor, a second terminal thereof is coupled to the first reference voltage, and a control terminal thereof receives the writing signal; an eighth transistor, wherein a first terminal thereof is coupled to the first terminal of the third transistor, a second terminal thereof is coupled to the gray-level voltage, and a control terminal thereof receives the writing signal; and a ninth transistor, wherein a first terminal thereof is coupled to the first terminal of the fourth transistor, a second terminal thereof is coupled to the second terminal of the capacitor, and a control terminal thereof receives the writing signal.
12. 12 . The pixel circuit according to claim 11 , wherein the first transistor to the ninth transistor are P-type transistors, the at least one reset signal is at a logical low level during the enabling period of the at least one reset signal, and the writing signal is at the logical low level during the enable period of the writing signal.
13. 13 . A driving method of a pixel circuit, comprising: controlling a reset circuit according to at least one reset signal to reset a voltage at a node based on at least one reference voltage, wherein the node is coupled to a capacitor; controlling a writing circuit according to a writing signal to write a gray-level voltage into the capacitor and change the voltage at the node to respond to a critical voltage; and controlling a driving circuit according to a driving signal to generate a driving current based on the voltage at the node and drive a light-emitting diode according to the driving current, wherein brightness of the light-emitting diode changes with the driving current, wherein an enabling period of the at least one reset signal partially overlaps with an enabling period of the writing signal, so that the gray-level voltage is written into the capacitor while the at least one reference voltage is applied to the node, wherein a duration of an enabling period of the writing signal is greater than a duration of an enabling period of the gray-level voltage.
14. 14 . The driving method according to claim 13 , wherein the enabling period of the at least one reset signal ends earlier than the enabling period of the writing signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of Taiwan application serial no. 113140734, filed on Oct. 25, 2024. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND Technical Field The disclosure relates to a pixel circuit applicable to a light-emitting diode. Description of Related Art In the related art, display panels are widely applied in various display apparatuses, and one of the core components is the pixel circuit. A pixel circuit typically includes multiple transistors, one or more capacitors, and a light-emitting diode (LED), and these components work together to achieve the function of image display. Each pixel circuit goes through multiple different operation periods during operation. For instance, during a specific period of time, a gray-level voltage is written and stored into a capacitor and then drives an LED to emit light. However, in some products, the time it takes to charge the capacitor is shortened. For instance, with the increase in display resolution and high refresh rate, the capacitor cannot be fully charged within a limited time. In addition, due to the capacitive coupling phenomenon in the pixel circuit, when the voltage on the data line changes, these changes may couple to the capacitor, causing the voltage in the pixel circuit to shift, so the display effect is thereby affected. SUMMARY The disclosure provides a pixel circuit and a driving method of the pixel circuit capable of solving the display abnormality problem caused by the voltage change on the data line when the charging time is excessively short. The disclosure provides a pixel circuit including a capacitor, a reset circuit, a writing circuit, a driving circuit, and a light-emitting diode. The capacitor is coupled to a node. The reset circuit is controlled by at least one reset signal and is configured to reset a voltage at the node based on at least one reference voltage. The writing circuit is controlled by a writing signal and is configured to write a gray-level voltage into the capacitor and change the voltage at the node to respond to a critical voltage. The driving circuit is controlled by a driving signal and is configured to generate a driving current based on the voltage at the node. The light-emitting diode is coupled to the driving circuit, and brightness of the light-emitting diode changes with the driving current. An enabling period of the reset signal partially overlaps with an enabling period of the writing signal, so that the gray-level voltage is written into the capacitor while the reference voltage is applied to the node. In an embodiment of the disclosure, the reference voltage includes a first reference voltage and a second reference voltage. The reset circuit includes a first transistor, a second transistor, and a third transistor. In the first transistor, a first terminal thereof is coupled to the first reference voltage, a second terminal thereof is coupled to a first terminal of the capacitor, and a control terminal thereof receives the reset signal. In the second transistor, a first terminal thereof is coupled to a second terminal of the capacitor, a second terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the reset signal. In the third transistor, a first terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the reset signal. In an embodiment of the disclosure, the reference voltage includes a first reference voltage and a second reference voltage. The reset signal includes a first reset signal and a second reset signal. The reset circuit includes a first transistor, a second transistor, and a third transistor. In the first transistor, a first terminal thereof is coupled to the first reference voltage, a second terminal thereof is coupled to a first terminal of the capacitor, and a control terminal thereof receives the first reset signal. In the second transistor, a first terminal thereof is coupled to a second terminal of the capacitor, a second terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the second reset signal. In the third transistor, a first terminal thereof is coupled to the second reference voltage, and a control terminal thereof receives the first reset signal. In an embodiment of the disclosure, an enabling period of the first reset signal does not overlap with the enabling period of the writing signal, and an enabling period of the second reset signal partially overlaps with the enabling period of the writing signal. In an embodiment of the disclosure, the writing circuit includes a fourth transistor and a fifth transistor. In the fourth transistor, a first terminal thereof is coupled to the gray-level voltage, a second terminal thereof is coupled to the first terminal of the capacitor, and a cont