US-12626633-B2 - Display panel with even and odd-numbered row pixel driving, a plurality of multiplexing circuits for data line driving and method for driving the same

US12626633B2US 12626633 B2US12626633 B2US 12626633B2US-12626633-B2

Abstract

The display panel includes a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, a same row of pixel circuits corresponds to two rows of gate lines, and one/the other row of gate line is electrically connected to odd/even-numbered columns of pixel circuits in the row of pixel circuits, and provides a corresponding gate driving signal for the odd/even-numbered columns of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one/the other column of data line of the two columns of data lines is electrically connected to odd/even-numbered rows of pixel circuits, and provides a corresponding data voltage for the odd/even-numbered rows of pixel circuits.

Inventors

Tian DONG
Jingquan WANG
Can ZHENG
Li Wang
Long Han
Yu Feng
Hao Zhang
Jiangnan Lu
Jie Zhang
Bo Wang

Assignees

BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240503

Claims (9)

1 . A driving method of a display panel, wherein the display panel comprises: a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, a plurality of rows of light-emitting control lines, and a plurality of columns of data lines, wherein a same row of pixel circuits corresponds to two rows of gate lines, and one row of gate line of the two rows of gate lines is electrically connected to only odd-numbered columns of pixel circuits in the row of pixel circuits, and is configured to provide a corresponding gate driving signal for only the odd-numbered columns of pixel circuits in the row of pixel circuits; the other row of gate line of the two rows of gate lines is electrically connected to only even-numbered columns of pixel circuits in the row of pixel circuits, and is configured to provide a corresponding gate driving signal for only the even-numbered columns of pixel circuits in the row of pixel circuits; the same row of pixel circuits corresponds to a row of reset control line, and the reset control lines provide a corresponding reset control signal for the row of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one column of data line of the two columns of data lines is electrically connected to odd-numbered rows of pixel circuits in the column of pixel circuits, and is configured to provide a corresponding data voltage for the odd-numbered rows of pixel circuits in the column of pixel circuits; and the other column of data line of the two columns of data lines is electrically connected to even-numbered rows of pixel circuits in the column of pixel circuits, and is configured to provide a corresponding data voltage for the even-numbered row of pixel circuits in the column of pixel circuits; wherein the display panel further comprises a plurality of multiplexing circuits, wherein a p-th multiplexing circuit is configured to control a data voltage provided by a p-th data input terminal to be input to four columns of data lines in a time-division manner under the control of a multiplexing control signal provided by a multiplexing control line; p is a positive integer; and wherein the multiplexing control line comprises a first multiplexing control line, a second multiplexing control line, a third multiplexing control line, and a fourth multiplexing control line, and the p-th multiplexing circuit comprises a p-th first multiplexing sub-circuit, a p-th second multiplexing sub-circuit, a p-th third multiplexing sub-circuit, and a p-th fourth multiplexing sub-circuit, wherein, the p-th first multiplexing sub-circuit is electrically connected to the first multiplexing control line, the p-th data input terminal, and the first column of data line, respectively, and controls to connect or disconnect the p-th data input terminal and the first column of data line under the control of a first multiplexing control signal provided on the first multiplexing control line; the p-th second multiplexing sub-circuit is electrically connected to the third multiplexing control line, the p-th data input terminal, and the second column of data line, respectively, and controls to connect or disconnect the p-th data input terminal and the second column of data line under the control of a third multiplexing control signal provided on the third multiplexing control line; the p-th third multiplexing sub-circuit is electrically connected to the fourth multiplexing control line, the p-th data input terminal, and the third column of data line, respectively, and controls to connect or disconnect the p-th data input terminal and the third column of data line under the control of a fourth multiplexing control signal provided on the fourth multiplexing control line; the p-th fourth multiplexing sub-circuit is electrically connected to the second multiplexing control line, the p-th data input terminal, and the fourth column of data line, respectively, and controls to connect or disconnect the p-th data input terminal and the fourth column of data line under the control of a second multiplexing control signal provided on the second multiplexing control line; wherein the method comprises: providing, by a same row of reset control line, a reset control signal for the same row of pixel circuits; providing, by one row of gate line of the two rows of gate lines corresponding to the same row of pixel circuits, a corresponding gate driving signal for the odd-numbered column of pixel circuits in the same row of pixel circuits, and providing, by the other row of gate line of the two rows of gate lines corresponding to the same row of pixel circuits, a corresponding gate driving signal for the even-numbered column of pixel circuits in the same row of pixel circuits; and providing, by one column of data line of the two columns of data lines corresponding to the same column of pixel circuits, a corresponding data voltage for the odd-numbered row of pixel circuits in the same column of pixel circuits, and providing, by the other column of data line of the two columns of data lines corresponding to the same column of pixel circuits, a corresponding data voltage for the even-numbered row of pixel circuits in the same column of pixel circuits, wherein a gate driving signal on a row of gate line is delayed by H/2 from a gate driving signal on an adjacent previous row of gate line, and H is a row period; wherein an n-th row display period comprises an n-th reset period, an n-th data writing-in period, and an n-th light-emitting control period that are sequentially set; n is a positive integer; in the n-th reset period, the n-th row of reset control signal line provides a valid n-th row of reset control signal; in a (2n-1)th row of writing-in period comprised in the n-th data writing-in period, a (2n -1)th row of gate line provides a valid gate driving signal; in an 2n-th row of writing time period comprised in the n-th data writing-in time period, a 2n-th row of gate line provides a valid gate driving signal; in the n-th light-emitting control period, the n-th row of light-emitting control line provides a valid light emitting control signal; the 2n-th row of writing-in period is delayed by H/2 from the (2n-1)th row of the writing-in period.
2 . The driving method of the display panel according to claim 1 , further comprising: providing, by a same row of the light-emitting control line, a light-emitting control signal for the same row of pixel circuits.
3 . The driving method of the display panel according to claim 1 , further comprising: controlling, by the multiplexing circuit, a data voltage provided by the data input terminal to be input to four columns of data lines in a time-division manner under the control of a multiplexing control signal provided by a multiplexing control line.
4 . The driving method of the display panel according to claim 3 , wherein a data providing period comprises a first data providing period, a second data providing period, a third data providing period and a fourth data providing period; the controlling, by the multiplexing circuit, a data voltage provided by the data input terminal to be input to four columns of data lines in a time-division manner under the control of a multiplexing control signal provided by a multiplexing control line comprises: in the first data providing period, the p-th first multiplexing sub-circuit controlling to connect the p-th data input terminal and the first column of data line under the control of the first multiplexing control signal provided by the first multiplexing control line; in the second data providing period, the p-th fourth multiplexing sub-circuit controlling to connect the p-th data input terminal and the fourth column of data line under the control of the second multiplexing control signal provided by the second multiplexing control line; in the third data providing period, the p-th second multiplexing sub-circuit controlling to connect the p-th data input terminal and the second column of data line under the control of the third multiplexing control signal provided by the third multiplexing control line; in the fourth data providing period, the p-th third multiplexing sub-circuit controlling to connect the p-th data input terminal and the third column of data line under the control of the fourth multiplexing control signal provided by the fourth multiplexing control line.
5 . A display device comprising a display panel, wherein the display panel comprises: a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, wherein a same row of pixel circuits corresponds to two rows of gate lines, and one row of gate line of the two rows of gate lines is electrically connected to only odd-numbered columns of pixel circuits in the row of pixel circuits, and is configured to provide a corresponding gate driving signal for only the odd-numbered columns of pixel circuits in the row of pixel circuits; the other row of gate line of the two rows of gate lines is electrically connected to only even-numbered columns of pixel circuits in the row of pixel circuits, and is configured to provide a corresponding gate driving signal for only the even-numbered columns of pixel circuits in the row of pixel circuits; the same row of pixel circuits corresponds to a row of reset control line, and the reset control lines provide a corresponding reset control signal for the row of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one column of data line of the two columns of data lines is electrically connected to odd-numbered rows of pixel circuits in the column of pixel circuits, and is configured to provide a corresponding data voltage for the odd-numbered rows of pixel circuits in the column of pixel circuits; and the other column of data line of the two columns of data lines is electrically connected to even-numbered rows of pixel circuits in the column of pixel circuits, and is configured to provide a corresponding data voltage for the even-numbered row of pixel circuits in the column of pixel circuits; wherein the display panel further comprises a plurality of multiplexing circuits, wherein a p-th multiplexing circuit is configured to control a data voltage provided by a p-th data input terminal to be input to four columns of data lines in a time-division manner under the control of a multiplexing control signal provided by a multiplexing control line; p is a positive integer; wherein the multiplexing control line comprises a first multiplexing control line, a second multiplexing control line, a third multiplexing control line, and a fourth multiplexing control line, and the p-th multiplexing circuit comprises a p-th first multiplexing sub-circuit, a p-th second multiplexing sub-circuit, a p-th third multiplexing sub-circuit, and a p-th fourth multiplexing sub-circuit, wherein, the p-th first multiplexing sub-circuit is electrically connected to the first multiplexing control line, the p-th data input terminal, and the first column of data line, respectively, and controls to connect or disconnect the p-th data input terminal and the first column of data line under the control of a first multiplexing control signal provided on the first multiplexing control line; the p-th second multiplexing sub-circuit is electrically connected to the third multiplexing control line, the p-th data input terminal, and the second column of data line, respectively, and controls to connect or disconnect the p-th data input terminal and the second column of data line under the control of a third multiplexing control signal provided on the third multiplexing control line; the p-th third multiplexing sub-circuit is electrically connected to the fourth multiplexing control line, the p-th data input terminal, and the third column of data line, respectively, and controls to connect or disconnect the p-th data input terminal and the third column of data line under the control of a fourth multiplexing control signal provided on the fourth multiplexing control line; the p-th fourth multiplexing sub-circuit is electrically connected to the second multiplexing control line, the p-th data input terminal, and the fourth column of data line, respectively, and controls to connect or disconnect the p-th data input terminal and the fourth column of data line under the control of a second multiplexing control signal provided on the second multiplexing control line; wherein display device further comprises: a first gate driving circuit, a second gate driving circuit, a third gate driving circuit, and a fourth gate driving circuit; wherein the first gate driving circuit is configured to provide a first row of gate driving signal for the first row of gate line; the second gate driving circuit is configured to provide a second row of gate driving signal for the second row of gate line; the third gate driving circuit is configured to provide a third row of gate driving signal for the third row of gate line; the fourth gate driving circuit is configured to provide a fourth row of gate driving signal for the fourth row of gate line; and wherein the first gate driving circuit comprises a plurality of stages of first shift register units; a gate driving signal output terminal of an a-th stage of first shift register unit is electrically connected to the first row of gate line, and an input terminal of a (a+1)th stage of first shift register unit is electrically connected to the first row of gate line, a gate driving signal output terminal of the (a+1)th stage of the first shift register unit is electrically connected to the fifth row of gate line; a reset terminal of the a-th stage of first shift register unit is electrically connected to the fifth row of gate line; a is a positive integer; the second gate driving circuit comprises a plurality of stages of second shift register units; a gate driving signal output terminal of an a-th stage of second shift register unit is electrically connected to the second row of gate line, and an input terminal of a (a+1)th stage of the second shift register unit is electrically connected to the second row of gate line, a gate driving signal output terminal of the (a+1)th stage of second shift register unit is electrically connected to the sixth row of gate line; a reset terminal of the a-th stage of second shift register unit is electrically connected to the sixth row of gate line; the third gate driving circuit comprises a plurality of stages of third shift register units; a gate driving signal output terminal of an a-th stage of third shift register unit is electrically connected to the third row of gate line, and an input terminal of a (a+1)th stage of second shift register unit is electrically connected to the third row of gate line, a gate driving signal output terminal of the (a+1)th stage of third shift register unit is electrically connected to the seventh row of gate line; a reset terminal of the a-th stage of third shift register unit is electrically connected to the seventh row of gate line, the fourth gate driving circuit comprises a plurality of stages of fourth shift register units; a gate driving signal output terminal of an a-th stage of fourth shift register unit is electrically connected to the fourth row of gate line, and an input terminal of a (a+1)th stage of fourth shift register unit is electrically connected to the fourth row of gate line; a gate driving signal output terminal of the (a+1)th stage of fourth shift register unit is electrically connected to the eighth row of gate line; a reset terminal of the a-th stage of fourth shift register unit is electrically connected to the eighth row of gate line.
6 . The display device according to claim 5 , wherein the display device further comprises a reset control signal generating circuit, the reset control signal generating circuit is configured to provide a corresponding reset control signal for each row of reset control line.
7 . The display device according to claim 5 , wherein the display panel further comprises a plurality of rows of light emitting control lines; the display device further comprises a light emitting control signal generation circuit; the light emitting control signal generation circuit is configured to provide a corresponding light-emitting control signal for each row of light-emitting control line.
8 . The display device according to claim 5 , wherein a gate driving signal on a row of gate line is delayed by H/2 from a gate driving signal on an adjacent previous row of gate line, and H is a row period.
9 . The display device according to claim 5 , wherein the p-th first multiplexing sub-circuit comprises a p-th first multiplexing transistor, the p-th second multiplexing sub-circuit comprises a p-th second multiplexing transistor, and the p-th third multiplexing sub-circuit comprises a p-th third multiplexing transistor, and the p-th fourth multiplexing sub-circuit comprises a p-th fourth multiplexing transistor; a control electrode of the p-th first multiplexing transistor is electrically connected to the first multiplexing control line, and a first electrode of the p-th first multiplexing transistor is electrically connected to the p-th data input terminal, a second electrode of the p-th first multiplexing transistor is electrically connected to the first column of data line; a control electrode of the p-th second multiplexing transistor is electrically connected to the third multiplexing control line, and a first electrode of the p-th second multiplexing transistor is electrically connected to the p-th data input terminal, a second electrode of the p-th second multiplexing transistor is electrically connected to the second column of data line; a control electrode of the p-th third multiplexing transistor is electrically connected to the fourth multiplexing control line, and a first electrode of the p-th third multiplexing transistor is electrically connected to the p-th data input terminal, a second electrode of the p-th third multiplexing transistor is electrically connected to the third column of data line; a control electrode of the p-th fourth multiplexing transistor is electrically connected to the second multiplexing control line, and a first electrode of the p-th fourth multiplexing transistor is electrically connected to the p-th data input terminal, a second electrode of the p-th fourth multiplexing transistor is electrically connected to the fourth column of data line.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a divisional of U.S. patent application Ser. No. 17/594,771, entitled “DISPLAY PANEL, METHOD FOR DRIVING THE SAME, AND DISPLAY DEVICE”, filed on Oct. 28, 2021, which is the U.S. National Phase of PCT Application No. PCT/CN2020/125363, entitled “DISPLAY PANEL, METHOD FOR DRIVING THE SAME, AND DISPLAY DEVICE’, filed on Oct. 30, 2020, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the field of display technology, in particular to a display panel, a method for driving the same and a display device. BACKGROUND Currently, Virtual Reality (VR) displays and gaming phones that are in greater demand on the market require a higher refresh rate of display panel. When the refresh rate of the display panel is increased to a predetermined speed, the conventional driving method has the problem of insufficient threshold voltage compensation capability, which will cause uneven display of the display panel. SUMMARY In a first aspect, the present disclosure provides in some embodiments a display panel including a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, wherein a same row of pixel circuits corresponds to two rows of gate lines, and one row of gate line of the two rows of gate lines is electrically connected to odd-numbered columns of pixel circuits in the row of pixel circuits, and is configured to provide a corresponding gate driving signal to for the odd-numbered columns of pixel circuits in the row of pixel circuits; the other row of gate line of the two rows of gate lines is electrically connected to even-numbered columns of pixel circuits in the row of pixel circuits, and is configured to provide a corresponding gate driving signal for the even-numbered columns of pixel circuits in the row of pixel circuits; the same row of pixel circuits corresponds to a row of reset control line, and the reset control lines provide a corresponding reset control signal for the row of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one column of data line of the two columns of data lines is electrically connected to odd-numbered rows of pixel circuits in the column of pixel circuits, and is configured to provide a corresponding data voltage for the odd-numbered rows of pixel circuits in the column of pixel circuits; and the other column of data line of the two columns of data lines is electrically connected to even-numbered rows of pixel circuits in the column of pixel circuits, and is configured to provide a corresponding data voltage for the even-numbered row of pixel circuits in the column of pixel circuits. Optionally, a gate driving signal on a row of gate line is delayed by H/2 from a gate driving signal on an adjacent previous row of gate line, and H is a row period. Optionally, the display panel further includes a plurality of multiplexing circuits, the multiplexing circuit is configured to control a data voltage provided by a p-th data input terminal to be input to four columns of data lines in a time-division manner under the control of a multiplexing control signal provided by a multiplexing control line; p is a positive integer. Optionally, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a first column gate control line, and a second column gate control line; a p-th multiplexing circuit includes a p-th row of multiplexing sub-circuit and a p-th of column multiplexing sub-circuit; the p-th column of multiplexing sub-circuit is respectively electrically connected to the p-th data input terminal, the first column gate control line, the second column gate control line, a (2p−1)th writing-in node and a 2p-th writing-in node, configured for controlling to connect or disconnect the p-th data input terminal and the (2p−1)th writing-in node, and connect or disconnect the p-th data input terminal and the 2p-th writing-in node under the control of the first column gate control signal provided by the first column gate control line and the second column gate control signal provided by the second column gate control line; the p-th row of multiplexing sub-circuit is electrically respectively connected to the (2p−1)th writing-in node, the 2p-th writing-in node, the first multiplexing control line, the second multiplexing control line, the first column of data line, the second column of data line, the third column of data line and the fourth column of data line, and configured for controlling the (2p−1)th writing-in node to connect to the first column of data line or the second column of data line, and the 2p-th writing-in node to connect to the third column of data line or the fourth column of data line under the control of the first multiplexing control signal provided b