US-12626634-B2 - Display driving device, processor, and electronic system

US12626634B2US 12626634 B2US12626634 B2US 12626634B2US-12626634-B2

Abstract

An electronic system may include a processor configured to output image data corresponding to an original image having a first resolution and a synchronization signal; and a display driving device configured to generate a result image having a higher than the first resolution, based on the image data and the synchronization signal, the image data including line image data corresponding to horizontal lines of the original image, and the synchronization signal including horizontal synchronization signals output at horizontal periods, the horizontal synchronization signals including active synchronization signals determining output timing of the line image data, and blank synchronization signals unrelated to the line image data, and the processor configured to output at least one of the blank synchronization signals between at least some of the active synchronization signals, based on scaling information determined based on the first resolution and the second resolution.

Inventors

Jiyu Park
Kyounghwan KWON
Yonjun Shin
Junghak Lee

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240828

Claims (19)

1 . An electronic system comprising: a processor configured to output a synchronization signal and image data corresponding to an original image having a first resolution; and a display driving circuit configured to, based on the image data and the synchronization signal, generate a result image being displayed on a display panel, the result image having a second resolution, higher than the first resolution, the image data including a plurality of line image data corresponding to horizontal lines of the original image, and the synchronization signal including a plurality of horizontal synchronization signals output at horizontal periods, the plurality of horizontal synchronization signals including a plurality of active synchronization signals determining output timing of the plurality of line image data, and a plurality of blank synchronization signals unrelated to the plurality of line image data, wherein a number of the plurality of blank synchronization signals is equal to a number of horizontal lines in the result image less a number of horizontal lines in the original image, and the processor configured to output at least one of the plurality of blank synchronization signals between at least some of the plurality of active synchronization signals, based on scaling information determined based on the first resolution and the second resolution, wherein the display driving circuit includes an image scaling circuit configured to generate the result image based on upscaling the original image, wherein the image scaling circuit is configured to determine an output timing of the plurality of blank synchronization signals and the number of the plurality of blank synchronization signals.
2 . The electronic system of claim 1 , wherein the synchronization signal further includes a vertical synchronization signal determining a frame period, and the number of horizontal lines in the original image is equal to a number of times at which the processor is configured to output active synchronization signals during one frame period.
3 . The electronic system of claim 2 , wherein the processor is configured to consecutively output two or more of the plurality of active synchronization signals when the vertical synchronization signal is output and the frame period begins.
4 . The electronic system of claim 1 , wherein the processor is configured to match and output the plurality of line image data to the plurality of active synchronization signals, respectively.
5 . The electronic system of claim 4 , wherein the processor is configured to determine a horizontal period in response to adjusting a porch section of an original horizontal period determined based on the first resolution, and the processor is configured to adjust the porch section based on the scaling information.
6 . The electronic system of claim 5 , wherein the processor is configured to adjust a length of at least one of a back porch section before an active section of the original horizontal period and a front porch section after the active section.
7 . The electronic system of claim 1 , wherein the processor includes: a storage configured to store the scaling information; a video timing circuit configured to generate control data including an output timing of the plurality of blank synchronization signals and a number of the plurality of blank synchronization signals based on the scaling information; and a packet generating circuit configured to output the plurality of active synchronization signals, the plurality of line image data, and the plurality of blank synchronization signals to the display driving circuit based on the control data.
8 . A display driving device comprising: a data receiving circuit configured to receive display data including image data and a synchronization signal from an external host; and an image scaling circuit configured to upscale resolution of the image data based on a plurality of horizontal synchronization signals included in the synchronization signal and transmitted at horizontal periods, the plurality of horizontal synchronization signals including a plurality of active synchronization signals transmitted in synchronization with a plurality of line image data corresponding to a plurality of horizontal lines included in the image data, and a plurality of blank synchronization signals unrelated to the plurality of line image data, wherein a number of the plurality of blank synchronization signals is equal to a number of horizontal lines of the upscaled resolution of the image data less a number of the plurality of horizontal lines included in the image data, and the image scaling circuit is configured to generate a plurality of additional line image data synchronized to the plurality of blank synchronization signals, based on at least one of the plurality of line image data transmitted in synchronization with at least one of the plurality of active synchronization signals.
9 . The display driving device of claim 8 , further comprising: a gate driver configured to drive a plurality of pixels included in a display panel; a source driver configured to determine data signal based on the plurality of line image data and the plurality of additional line image data, and to output the data signal to the plurality of pixels; and a timing controller configured to control operation timing of the gate driver and the source driver based on the plurality of horizontal synchronization signals.
10 . The display driving device of claim 9 , wherein the source driver is configured to output the data signal during an active section included in a horizontal period of each of the plurality of horizontal synchronization signals, the horizontal period further including a back porch section before the active section, and a front porch section after the active section, and a length of the front porch section is different from a length of the back porch section.
11 . The display driving device of claim 10 , wherein the length of the front porch section is longer than the length of the back porch section.
12 . The display driving device of claim 10 , wherein the image scaling circuit is configured to generate pixel data output to the display panel based on the source driver, during at least a portion of the front porch section of each of the plurality of active synchronization signals.
13 . The display driving device of claim 12 , wherein the timing controller is configured to control the gate driver and the source driver based on a front porch section of an internal horizontal synchronization signal, the front porch section of each of the plurality of active synchronization signals being longer than the front porch section of the internal horizontal synchronization signal.
14 . The display driving device of claim 8 , wherein the image data has first resolution, and a result image output to a display panel has second resolution, higher than the first resolution.
15 . A processor comprising: a storage configured to store scaling information received externally, wherein the scaling information includes a number of horizontal lines in a result image; a video timing circuit configured to generate a vertical synchronization signal and a horizontal synchronization signal based on the scaling information; a packet generating circuit configured to generate a plurality of data packets within one period of the vertical synchronization signal; and an image processing circuit configured to output an original image including a plurality of line image data arranged along a plurality of horizontal lines to the packet generating circuit wherein the packet generating circuit is configured to generate a portion of the plurality of data packets based on matching active synchronization signals included in the horizontal synchronization signal with the plurality of line image data, respectively, and generate a remainder of the plurality of data packets using blank synchronization signals included in the horizontal synchronization signal, wherein a number of the blank synchronization signals is equal to the number of the horizontal lines in the result image less a number of the plurality of horizontal lines in the original image.
16 . The processor of claim 15 , wherein the video timing circuit is configured to generate the vertical synchronization signal and the horizontal synchronization signal based on first scaling information while the image processing circuit outputs a first frame of the original image, and the video timing circuit is configured to generate the vertical synchronization signal and the horizontal synchronization signal based on second scaling information different from the first scaling information while the image processing circuit outputs a second frame following the first frame of the original image.
17 . The processor of claim 16 , wherein the storage includes first storage and second storage, and wherein the first storage is configured to store the first scaling information and the second storage is configured to store the second scaling information while the image processing circuit outputs the first frame.
18 . The processor of claim 16 , wherein the video timing circuit is configured to output the active synchronization signals and the blank synchronization signals according to a first sequence while the packet generating circuit receives the first frame from the image processing circuit, and the video timing circuit is configured to output the active synchronization signals and the blank synchronization signals according to a second sequence different from the first sequence while the packet generating circuit receives the second frame from the image processing circuit.
19 . The processor of claim 18 , wherein a number of times at which the blank synchronization signals are output according to the first sequence is equal to a number of times at which the blank synchronization signals are output according to the second sequence.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims benefit of priority to Korean Patent Application No. 10-2024-0029008 filed on Feb. 28, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND The present disclosure relate to display driving devices, processors, and electronic systems. By utilizing technology to upscale a relatively low-resolution original image and output a result image having high resolution to a display, internal storage capacitance of an electronic device may be reduced and a high-quality result image may be provided to a user. A processor generates a result image after completing an upscaling process, and a display driving device receives the result image and outputs the result image to a display panel, from which an upscaling function may be implemented. However, in this method, the amount of data transmitted and power consumption between the processor and the display driving device may increase. The upscaling function may be implemented in the display driving device to reduce an increase in the amount of data transmitted and the power consumption, but in this case, the display driving device must include an internal memory such as a buffer that may store an original image, which may lead to a decrease in the integration of the display driving device and an increase in manufacturing costs. SUMMARY Some aspects of the present disclosure are to provide display driving devices, processors, and electronic systems which may implement an upscaling function without a memory for storing an original image while minimizing an increase in the amount of data transmitted between a processor and a display driving device. According to some example embodiments of the present disclosure, an electronic system includes a processor configured to output a synchronization signal, and image data corresponding to an original image having a first resolution; and a display driving device configured to generate a result image having a second resolution, higher than the first resolution, based on the image data and the synchronization signal, the image data including a plurality of line image data corresponding to horizontal lines of the original image and the synchronization signal including a plurality of horizontal synchronization signals output at horizontal periods, the plurality of horizontal synchronization signals include a plurality of active synchronization signals determining output timing of the plurality of line image data, and a plurality of blank synchronization signals unrelated to the plurality of line image data, and the processor configured to output at least one of the blank synchronization signals between at least some of the active synchronization signals, based on scaling information determined based on the first resolution and the second resolution. According to some example embodiments of the present disclosure, a display driving device includes a receiver configured to receive display data including image data and a synchronization signal from an external host; and an image scaler configured to upscale resolution of the image data based on a plurality of horizontal synchronization signals included in the synchronization signal and transmitted at horizontal periods, the plurality of horizontal synchronization signals including a plurality of active synchronization signals transmitted in synchronization with a plurality of line image data corresponding to a plurality of horizontal lines included in the image data, and a plurality of blank synchronization signals unrelated to the plurality of line image data, and the image scaler is configured to generate a plurality of additional line image data synchronized to the plurality of blank synchronization signals, based on at least one line image data transmitted in synchronization with at least one of the plurality of active synchronization signals. According to some example embodiments of the present disclosure, a processor includes storage configured to store scaling information received externally; a video timer configured to generate a vertical synchronization signal and a horizontal synchronization signal based on the scaling information; a packet generator configured to generate a plurality of data packets inside one period of the vertical synchronization signal; and an image processing logic configured to output an original image including a plurality of line image data arranged along a plurality of horizontal lines to the packet generator, the packet generator configured to generate a portion of the plurality of data packets based on matching active synchronization signals included in the horizontal synchronization signal with the plurality of line image data, respectively, and generate a remainder of the plurality of data packets using blank synchronization signals included in the horizontal synchronization signal. According to some examp