US-12626639-B2 - Display panel and display apparatus

Abstract

A display panel includes a first sub-region and a second sub-region, a non-display region, a first pixel circuit in the first sub-region, a second pixel circuit in the second sub-region, a first data line at least in the first sub-region, a second data line at least in the second sub-region, and a control circuit in the non-display region and connected to the first data line and the second data line. The first data line is electrically connected to the first pixel circuit. The second data line is electrically connected to the second pixel circuit. In a first mode, a data voltage refresh frequency of the first sub-region is different from that of the second sub-region, the control circuit writes a voltage to the first data line in scanning of the first sub-region and writes a voltage to the second first data line in scanning of the second sub-region.

Inventors

• Mengmeng ZHANG

Assignees

• WUHAN TIANMA MICROELECTRONICS CO., LTD.
• Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch

Dates

Publication Date

20260512

Application Date

20240321

Priority Date

20230726

Claims (18)

1. 1 . A display panel, comprising: a display region comprising: a first sub-region; and a second sub-region; a non-display region; pixel circuits comprising: a first pixel circuit located in the first sub-region; and a second pixel circuit located in the second sub-region; data lines comprising a first data line and a second data line, wherein the first data line is at least located in the first sub-region and only electrically connected to the first pixel circuit, and the second data line is at least located in the second sub-region and only electrically connected to the second pixel circuit; and control circuits located in the non-display region, wherein a control circuit of the control circuits is electrically connected to the first data line and the second data line, wherein the display panel comprises a first mode, in the first mode, a data voltage refresh frequency of the first sub-region is a first frequency, a data voltage refresh frequency of the second sub-region is a second frequency, the first frequency is different from the second frequency, the control circuit is configured to write a voltage to the first data line during scanning of the first sub-region, and write a voltage to the second data line during scanning of the second sub-region; wherein the control circuit is located on a side of the non-display region adjacent to the second sub-region and electrically connected to the first data line through a connection line, and the connection line is at least located in the second sub-region; and wherein each pixel circuit comprises a driving transistor and a threshold compensation transistor, the threshold compensation transistor comprises a first electrode and a second electrode, a gate electrode of the driving transistor is electrically connected to the second electrode of the threshold compensation transistor through an auxiliary connection segment, and the auxiliary connection segment and the second electrode of the threshold compensation transistor are connected at a first connection node, and wherein the connection line comprises a first segment located in the second sub-region and extending in a same direction as the second data line, a minimum distance between the first connection node in the second pixel circuit and the first segment is greater than a minimum distance between the first connection node in the second pixel circuit and the second data line.
2. 2 . The display panel according to claim 1 , wherein the second frequency is greater than the first frequency.
3. 3 . The display panel according to claim 1 , wherein a layer of the first segment is located on a side of a layer of the auxiliary connection segment toward a light-emitting direction of the display panel.
4. 4 . The display panel according to claim 3 , wherein the pixel circuits are electrically connected to power supply signal lines, the power supply signal lines comprise a first power supply line and a second power supply line that are electrically connected to each other, and the first power supply line and the second power supply line extend in the same direction as the second data line, and wherein the first power supply line is disposed in a same layer as the auxiliary connection segment, a layer of the second power supply line is located on a side of the layer of the first power supply line toward the light-emitting direction of the display panel, and the first segment is disposed in a same layer as the second power supply line, or wherein the first power supply line is disposed in a same layer as the auxiliary connection segment, a layer of the second power supply line is located on a side of the layer of the first power supply line toward the light-emitting direction of the display panel, and a layer of the first segment is located on a side of the layer of the second power supply line toward the light-emitting direction of the display panel.
5. 5 . The display panel according to claim 1 , wherein the first data line comprises a first end adjacent to the second data line, and wherein the connection line extends in the same direction as the second data line, one end of the connection line is connected to the control circuit, and the other end of the connection line is adjacent to the first end and is connected to the first end through a first connector.
6. 6 . The display panel according to claim 5 , further comprising first wirings located in the first sub-region, wherein at least one of the first wirings is arranged in an extension direction of the connection line, wherein the first wirings receive a fixed voltage.
7. 7 . The display panel according to claim 1 , wherein the first data line comprises a second end away from the second data line, and wherein one end of the connection line is connected to the control circuit, and the other end of the connection line is adjacent to the second end and is connected to the second end through a second connector.
8. 8 . The display panel according to claim 7 , wherein the first data line further comprises a first end adjacent to the second data line, and wherein the connection line is further electrically connected to the first end through a third connector.
9. 9 . The display panel according to claim 7 , wherein the second connector and the second end are connected by a first conductive via, the second connector and the connection line are connected by a second conductive via, and the first conductive via and the second conductive via are located on a side of the non-display region adjacent to the first sub-region.
10. 10 . The display panel according to claim 1 , wherein the control circuit comprises a first switch and a second switch, input terminals of the first switch and the second switch are both electrically connected to a first source signal line, an output terminal of the first switch is electrically connected to the first data line, and an output terminal of the second switch is electrically connected to the second data line, and wherein the first switch is turned on during the scanning of the first sub-region, and the second switch is turned on during scanning of the second sub-region.
11. 11 . The display panel according to claim 1 , wherein the control circuit comprises a third switch, the second data line and an input terminal of the third switch are both electrically connected to a first source signal line, an output terminal of the third switch is electrically connected to the first data line, and wherein the third switch is turned on during the scanning of the first sub-region, and the second frequency is greater than the first frequency.
12. 12 . The display panel according to claim 1 , wherein the first pixel circuit comprises a plurality of first pixel circuits, the second pixel circuit comprises a plurality of second pixel circuits, the first data line comprises a plurality of first data lines, and the second data line comprises a plurality of second data lines, wherein the plurality of first pixel circuits are arranged in first circuit groups located in the first sub-region, the plurality of second pixel circuits are arranged in second circuit groups located in the second sub-region, each first circuit group comprises first pixel circuits arranged in a first direction, each second circuit group comprises second pixel circuits arranged in the first direction, and the first sub-region and the second sub-region are arranged in the first direction, wherein one of the first circuit groups is electrically connected to two of the first data lines, and one of the second circuit groups is electrically connected to two of the second data lines, wherein the control circuits comprise at least one switch group, each switch group corresponds to one of the first circuit groups and one of the second circuit groups and comprises two fourth switches and two fifth switches, input terminals of the two fourth switches and input terminals of the two fifth switches are electrically connected to a first source signal line, output terminals of the two fourth switches are electrically connected to two first data lines connected to the first circuit group corresponding to the switch group, and output terminals of the two fifth switches are electrically connected to two second data lines connected to the second circuit group corresponding to the switch group, wherein at least two of the fourth switches in the control circuits are turned on in the scanning of the first sub-region, and at least two of the fifth switches in the control circuits are turned on during the scanning of the second sub-region, and wherein the at least one switch group comprises at least two switch groups, the input terminals of the fourth switches and the input terminals of the fifth switches in the at least two switch groups are electrically connected to the first source signal line.
13. 13 . The display panel according to claim 1 , further comprising a gating circuit, wherein the gating circuit is electrically connected to at least two control circuits of the control circuits, and is configured to transmit a voltage to the at least two control circuits in a time division manner.
14. 14 . The display panel according to claim 1 , wherein each pixel circuit further comprises a data writing transistor, the data writing transistor is electrically connected to a first scan signal line and a first electrode of the driving transistor, the data writing transistor of the first pixel circuit is further electrically connected to the first data line, and the data writing transistor of the second pixel circuit is further electrically connected to the second data line, wherein the second frequency is greater than the first frequency, and in the first mode, and the scanning of the first sub-region and the scanning of the second sub-region are performed at the second frequency via the first scan signal line, wherein, in the first mode, a driving process of the first pixel circuit comprises a refreshing phase and a holding phase, a driving process of the second pixel circuit at least comprises a refreshing phase, a driving process of the display panel comprises a first frame and a second frame, in the first frame, the first pixel circuit and the second pixel circuit are in their refreshing phases, and in the second frame, the first pixel circuit is in the holding phase, and the second pixel circuit is in the refreshing phase, wherein, in the first frame, the control circuit writes a first data voltage to the first data line when the first scan signal line scans the first sub-region, and writes a second data voltage to the second data line when the first scan signal line scans the second sub-region, and wherein, in the second frame, the control circuit writes a preset voltage to the first data line when the first scan signal line scans the first sub-region, and writes the second data voltage to the second data line when the first scan signal line scans the second sub-region.
15. 15 . The display panel according to the claim 14 , wherein, in the first mode, the driving process of the second pixel circuit further comprises a holding phase, the driving process of the display panel further comprises a third frame, and in the third frame, the first pixel circuit and the second pixel circuit are in their holding phases, and wherein, in the third frame, the control circuit writes the preset voltage to the first data line when the first scan signal line scans the first sub-region, and writes the preset voltage to the second data line when the first scan signal line scans the second sub-region.
16. 16 . The display panel according to claim 1 , wherein each pixel circuit further comprises a bias transistor, the bias transistor is electrically connected to a second scan signal line and a first electrode of the driving transistor, the bias transistor of the first pixel circuit is further electrically connected to a first bias signal line, and the bias transistor of the second pixel circuit is further electrically connected to a second bias signal line, wherein, in the first mode, a driving process of the first pixel circuit comprises a refreshing phase and a holding phase, and a driving process of the second pixel circuit comprises a refreshing phase and a holding phase, and wherein, in the first mode, the first bias signal line provides different bias voltages in the refreshing phase and the holding phase of the first pixel circuit, and the second bias signal line provides different bias voltages in the refreshing phase and the holding phase of the second pixel circuit.
17. 17 . The display panel according to claim 1 , wherein each pixel circuit further comprises an anode reset transistor, the anode reset transistor is electrically connected to a second scan signal line and an anode of a light-emitting element, the anode reset transistor in the first pixel circuit is further electrically connected to a first anode reset signal line, and the anode reset transistor in the second pixel circuit is further electrically connected to a second anode reset signal line, wherein, in the first mode, a driving process of the first pixel circuit comprises a refreshing phase and a holding phase, and a driving process of the second pixel circuit comprises a refreshing phase and a holding phase, and wherein the first anode reset signal line provides different anode reset voltages in the refreshing phase and the holding phase of the first pixel circuit, and the second anode reset signal line provides different anode reset voltages in the refreshing phase and the holding phase of the second pixel circuit.
18. 18 . A display apparatus, comprising a display panel, wherein the display panel comprises: a display region comprising: a first sub-region; and a second sub-region; a non-display region; pixel circuits comprising: a first pixel circuit located in the first sub-region; and a second pixel circuit located in the second sub-region; data lines comprising a first data line and a second data line, wherein the first data line is at least located in the first sub-region and only electrically connected to the first pixel circuit, the second data line is at least located in the second sub-region and only electrically connected to the second pixel circuit; and control circuits located in the non-display region, wherein a control circuit of the control circuits is electrically connected to the first data line and the second data line, wherein the display panel comprises a first mode, in the first mode, a data voltage refresh frequency of the first sub-region is a first frequency, a data voltage refresh frequency of the second sub-region is a second frequency, the first frequency is different from the second frequency, the control circuit is configured to write a voltage to the first data line during scanning of the first sub-region, and write a voltage to the second data line during scanning of the second sub-region; wherein the control circuit is located on a side of the non-display region adjacent to the second sub-region and electrically connected to the first data line through a connection line, and the connection line is at least located in the second sub-region; and wherein each pixel circuit comprises a driving transistor and a threshold compensation transistor, the threshold compensation transistor comprises a first electrode and a second electrode, a gate electrode of the driving transistor is electrically connected to the second electrode of the threshold compensation transistor through an auxiliary connection segment, and the auxiliary connection segment and the second electrode of the threshold compensation transistor are connected at a first connection node, and wherein the connection line comprises a first segment located in the second sub-region and extending in a same direction as the second data line, a minimum distance between the first connection node in the second pixel circuit and the first segment is greater than a minimum distance between the first connection node in the second pixel circuit and the second data line.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present disclosure claims priority to Chinese patent application Ser. No. 202310927155.9, filed on Jul. 26, 2023, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display apparatus. BACKGROUND In some display modes, a display panel is driven at different frequencies and in different sub-regions. For example, a first sub-region is driven at 0.1 Hz to 1 Hz to display static images such as time information, while a second sub-region is driven at 10 Hz to 60 Hz to display dynamic images such as videos. When this display mode is applied, in order to ensure normal display of the sub-region with a higher refreshing frequency, data voltages on data lines are continuously refreshed at a high frequency. However, the data voltage on the data line may jump at a high frequency due to the coupling capacitance, so that a significant fluctuation occurs in a gate potential of a driving transistor of a pixel circuit in the sub-region with a lower refreshing frequency, resulting in adverse phenomena such as flickering images shown in the sub-region with a lower refreshing frequency. For example, when the first sub-region is driven by 1 Hz and the second sub-region is driven by 10 Hz, the data voltage on the data line jumps at a high frequency of 10 Hz, so that the static image of the first sub-region is affected by coupling, resulting in flickering images of the first sub-region. SUMMARY One aspect of the present disclosure provides a display panel. In an embodiment, the display panel includes a display region including a first sub-region and a second sub-region, a non-display region, pixel circuits including a first pixel circuit and a second pixel circuit, data lines including a first data line and a second data line, and control circuits located in the non-display region. In an embodiment, the first pixel circuit is located in the first sub-region, and the second pixel circuit is located in the second sub-region. In an embodiment, the first data line is at least located in the first sub-region and is electrically connected to the first pixel circuit, and the second data line is at least located in the second sub-region and is electrically connected to the second pixel circuit. In an embodiment, a control circuit of the control circuits is electrically connected to the first data line and the second data line. In an embodiment, the display panel has a first mode. In an embodiment, in the first mode, a data voltage refresh frequency of the first sub-region is a first frequency, a data voltage refresh frequency of the second sub-region is a second frequency, the first frequency is different from the second frequency, the control circuit is configured to write a voltage to the first data line in the scanning of the first sub-region and write a voltage to second first data line in the scanning of the second sub-region. Another aspect of the present disclosure provides a display apparatus. In an embodiment, the display apparatus includes a display panel. In an embodiment, the display panel includes a display region including a first sub-region and a second sub-region, a non-display region, pixel circuits including a first pixel circuit and a second pixel circuit, data lines including a first data line and a second data line, and control circuits located in the non-display region. In an embodiment, the first pixel circuit is located in the first sub-region, and the second pixel circuit is located in the second sub-region. In an embodiment, the first data line is at least located in the first sub-region and is electrically connected to the first pixel circuit, and the second data line is at least located in the second sub-region and is electrically connected to the second pixel circuit. In an embodiment, a control circuit of the control circuits is electrically connected to the first data line and the second data line. In an embodiment, the display panel has a first mode. In an embodiment, in the first mode, a data voltage refresh frequency of the first sub-region is a first frequency, a data voltage refresh frequency of the second sub-region is a second frequency, the first frequency is different from the second frequency, the control circuit is configured to write a voltage to the first data line in the scanning of the first sub-region and write a voltage to second first data line in the scanning of the second sub-region. BRIEF DESCRIPTION OF DRAWINGS In order to more clearly illustrate technical solutions of embodiments of the present disclosure, the accompanying drawings used in the embodiments are briefly described below. The drawings described below are merely a part of the embodiments of the present disclosure. Based on these drawings, those skilled in the art can obtain other drawings. FIG. 1 is a top view of a display panel acco