US-12626650-B2 - Pixel of a display device, and display device

Abstract

A pixel includes a first transistor including a first and second gates, a first capacitor connected between a first node and a third node, a second capacitor connected between a fourth node and the third node, a second transistor receiving a first scan signal and connected between a data line and the first node, a third transistor receiving a second scan signal and connected between a reference voltage line and the first node, a fourth transistor receiving a third scan signal and connected between an initialization line and the third node, a fifth transistor receiving an emission signal and connected between a first power line and the second node, a sixth transistor receiving the second scan signal and connected between the fourth node and the second node, and a light emitting element connected between the third node and a second power line.

Inventors

• Jongsik Shim
• Soon-Gi KWON
• Donghyun Kim
• Junyoung Min
• Jun-Yong AN
• Chanyoung Yang
• Seunghee Lee
• Junwon Choi

Assignees

• SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date

20260512

Application Date

20241211

Priority Date

20240116

Claims (20)

1. 1 . A pixel of a display device, the pixel comprising: a first transistor including a first gate connected to a first node, a first terminal connected to a second node, a second terminal connected to a third node, and a second gate connected to a fourth node; a first capacitor including a first electrode connected to the first node, and a second electrode connected to the third node; a second capacitor including a first electrode connected to the fourth node, and a second electrode connected to the third node; a second transistor including a gate which receives a first scan signal, a first terminal connected to a data line which transfers a data voltage, and a second terminal connected to the first node; a third transistor including a gate which receives a second scan signal, a first terminal connected to a line which transfers a reference voltage, and a second terminal connected to the first node; a fourth transistor including a gate which receives a third scan signal, a first terminal connected to a line which transfers an initialization voltage, and a second terminal connected to the third node; a fifth transistor including a gate which receives an emission signal, a first terminal connected to a line which transfers a first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate which receives the second scan signal, a first terminal connected to the fourth node, and a second terminal connected to the second node; and a light emitting element connected between the third node, and a line which transfers a second power supply voltage.
2. 2 . The pixel of claim 1 , wherein the first capacitor stores a voltage difference between the data voltage and the initialization voltage, and wherein, in a compensation period, the second scan signal has an on-level while the first scan signal has an off-level to enable the second capacitor to store a threshold voltage of the first transistor.
3. 3 . The pixel of claim 1 , wherein, in a compensation period, the third transistor applies the reference voltage to the first node, the fourth transistor applies the initialization voltage to the third node, the sixth transistor diode-connects the first transistor by connecting the fourth node to the second node, and the second capacitor stores a threshold voltage of the first transistor in a diode connection manner.
4. 4 . The pixel of claim 3 , wherein the initialization voltage is higher than the reference voltage.
5. 5 . The pixel of claim 4 , wherein, in the compensation period, a negative gate-source voltage is applied to the first transistor, and the threshold voltage of the first transistor is shifted in a positive direction.
6. 6 . The pixel of claim 1 , wherein the first gate of the first transistor is a top gate located above an active region, and wherein the second gate of the first transistor is a bottom gate located under the active region.
7. 7 . The pixel of claim 1 , wherein the first gate of the first transistor is a bottom gate located under an active region, and wherein the second gate of the first transistor is a top gate located above the active region.
8. 8 . The pixel of claim 1 , wherein the third scan signal is the same as the second scan signal.
9. 9 . The pixel of claim 1 , further comprising: a seventh transistor including a gate which receives a fourth scan signal, a first terminal connected to the line which transfers the first power supply voltage, and a second terminal connected to the fourth node.
10. 10 . The pixel of claim 9 , wherein frame periods for the display device include a compensation frame period in which the pixel performs a threshold voltage compensation operation, and a non-compensation frame period in which the pixel does not perform the threshold voltage compensation operation.
11. 11 . The pixel of claim 10 , wherein the compensation frame period comprises: an initialization period in which the third node and the fourth node are initialized; a compensation period in which the threshold voltage compensation operation is performed to store a threshold voltage of the first transistor in the second capacitor; a writing period in which a voltage difference between the data voltage and the initialization voltage is stored in the first capacitor; and an emission period in which the light emitting element emits light.
12. 12 . The pixel of claim 11 , wherein, in the initialization period, the third scan signal and the fourth scan signal have an on-level, the first scan signal, the second scan signal and the emission signal have an off-level, the fourth transistor is turned on in response to the third scan signal having the on-level, and applies the initialization voltage to the third node, the seventh transistor is turned on in response to the fourth scan signal having the on-level, and applies the first power supply voltage to the fourth node, the third node is initialized based on the initialization voltage, and the fourth node is initialized based on the first power supply voltage.
13. 13 . The pixel of claim 11 , wherein, in the compensation period, the second scan signal and the third scan signal have an on-level, the first scan signal, the fourth scan signal and the emission signal have an off-level, the third transistor is turned on in response to the second scan signal having the on-level, and applies the reference voltage to the first node, the fourth transistor is turned on in response to the third scan signal having the on-level, and applies the initialization voltage to the third node, the sixth transistor is turned on in response to the second scan signal having the on-level, and diode-connects the first transistor by connecting the fourth node to the second node, and the second capacitor stores the threshold voltage of the first transistor in a diode connection manner.
14. 14 . The pixel of claim 11 , wherein, in the writing period, the first scan signal and the third scan signal have an on-level, the second scan signal, the fourth scan signal and the emission signal have an off-level, the second transistor is turned on in response to the first scan signal having the on-level, and applies the data voltage to the first node, the fourth transistor is turned on in response to the third scan signal having the on-level, and applies the initialization voltage to the third node, and the first capacitor stores the voltage difference between the data voltage and the initialization voltage.
15. 15 . The pixel of claim 10 , wherein the non-compensation frame period comprises: a writing period in which a voltage difference between the data voltage and the initialization voltage is stored in the first capacitor; and an emission period in which the light emitting element emits light, and wherein the non-compensation frame period does not include an initialization period and a compensation period.
16. 16 . The pixel of claim 9 , wherein the first through seventh transistors are n-type metal oxide semiconductor (NMOS) transistors.
17. 17 . The pixel of claim 9 , wherein the first transistor is an n-type metal oxide semiconductor (NMOS) transistor, and wherein at least one of the second through seventh transistors is a p-type metal oxide semiconductor (PMOS) transistor.
18. 18 . The pixel of claim 11 , wherein, in the emission period, the emission signal has an on-level, the first scan signal, the second scan signal, the third scan signal and the fourth scan signal have an off-level, the fifth transistor is turned on in response to the emission signal having the on-level, and connects the line which transfers the first power supply voltage and the second node, the first transistor generates a driving current based on the voltage difference between the data voltage and the initialization voltage stored in the first capacitor, and the threshold voltage of the first transistor stored in the second capacitor, and the light emitting element emits light based on the driving current.
19. 19 . A pixel of a display device, the pixel comprising: a first transistor including a first gate connected to a first node, a first terminal connected to a second node, a second terminal connected to a third node, and a second gate connected to a fourth node; a first capacitor including a first electrode connected to the first node, and a second electrode connected to the third node; a second capacitor including a first electrode connected to the fourth node, and a second electrode connected to the third node; a second transistor including a gate which receives a first scan signal, a first terminal connected to a data line which transfers a data voltage, and a second terminal connected to the first node; a third transistor including a gate which receives a second scan signal, a first terminal connected to a line which transfers a reference voltage, and a second terminal connected to the first node; a fourth transistor including a gate which receives a third scan signal, a first terminal connected to a line which transfers an initialization voltage, and a second terminal connected to the third node; a fifth transistor including a gate which receives an emission signal, a first terminal connected to a line which transfers a first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate which receives the second scan signal, a first terminal connected to the fourth node, and a second terminal connected to the second node; a seventh transistor including a gate which receives a fourth scan signal, a first terminal connected to the line which transfers the first power supply voltage, and a second terminal connected to the fourth node; and a light emitting element connected between the third node and a line which transfers a second power supply voltage, wherein the first capacitor stores a voltage difference between the data voltage and the initialization voltage, and wherein the second capacitor stores a threshold voltage of the first transistor in a diode connection manner.
20. 20 . An electronic device comprising: a display panel including a plurality of pixels; a data driver configured to provide a data voltage to each of the plurality of pixels; a scan driver configured to provide a first scan signal, a second scan signal and a third scan signal to each of the plurality of pixels; an emission driver configured to provide an emission signal to each of the plurality of pixels; and a controller configured to control the data driver, the scan driver and the emission driver, wherein each of the plurality of pixels comprises: a first transistor including a first gate connected to a first node, a first terminal connected to a second node, a second terminal connected to a third node, and a second gate connected to a fourth node; a first capacitor including a first electrode connected to the first node, and a second electrode connected to the third node; a second capacitor including a first electrode connected to the fourth node, and a second electrode connected to the third node; a second transistor including a gate which receives the first scan signal, a first terminal connected to a data line which transfers the data voltage, and a second terminal connected to the first node; a third transistor including a gate which receives the second scan signal, a first terminal connected to a line which transfers a reference voltage, and a second terminal connected to the first node; a fourth transistor including a gate which receives the third scan signal, a first terminal connected to a line which transfers an initialization voltage, and a second terminal connected to the third node; a fifth transistor including a gate which receives the emission signal, a first terminal connected to a line which transfers a first power supply voltage, and a second terminal connected to the second node; a sixth transistor including a gate which receives the second scan signal, a first terminal connected to the fourth node, and a second terminal connected to the second node; and a light emitting element connected between the third node and a line which transfers a second power supply voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This patent application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2024-0006576, filed on Jan. 16, 2024, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference in its entirety herein. 1. TECHNICAL FIELD Embodiments of the present inventive concept are directed to a display device, and more particularly to a pixel and a display device including the pixel. 2. DISCUSSION OF RELATED ART Display devices having a flat panel display are a category of visual display technology that a typically thin and light weight, in contrast with bulkier cathode ray tube (CRT) displays. Examples of the flat panel display include a liquid crystal display (LCD), a light-emitting-diode (LED) display and an organic-light-emitting-diode (OLED) display. A flat panel display includes multiple pixels for presenting an image. The pixel may include a storage capacitor, a scan transistor that transfers a data voltage to the storage capacitor in response to a scan signal, a driving transistor that generates a current based on the data voltage stored in the storage capacitor, and a light emitting element that emits light based on the current generated by the driving transistor. The pixel may not emit light with a desired luminance when a threshold voltage of the driving transistor has an improper level. A compensation operation may be performed that compensates the threshold voltage of the driving transistor to reduce a luminance error caused by the improper level. However, the compensation operation may use an excessive amount of power. Further, horizontal crosstalk may occur due to the configuration of the pixel, thereby reducing image quality. Thus, there is a need for a pixel that uses less power and provides higher quality images. SUMMARY Some embodiments provide a pixel having an increased image quality and reduced power consumption, and display device including the pixel. According to an embodiment, there is provided a pixel of a display device including first through seventh transistors, first and second capacitors and a light emitting element. The first transistor includes a first gate connected to a first node, a first terminal connected to a second node, a second terminal connected to a third node, and a second gate connected to a fourth node. The first capacitor includes a first electrode connected to the first node, and a second electrode connected to the third node. The second capacitor includes a first electrode connected to the fourth node, and a second electrode connected to the third node, a second transistor including a gate which receives a first scan signal, a first terminal connected to a data line which transfers a data voltage, and a second terminal connected to the first node. The third transistor includes a gate which receives a second scan signal, a first terminal connected to a line which transfers a reference voltage, and a second terminal connected to the first node. The fourth transistor includes a gate which receives a third scan signal, a first terminal connected to a line which transfers an initialization voltage, and a second terminal connected to the third node. The fifth transistor includes a gate which receives an emission signal, a first terminal connected to a line which transfers a first power supply voltage, and a second terminal connected to the second node. The sixth transistor includes a gate which receives the second scan signal, a first terminal connected to the fourth node, and a second terminal connected to the second node. The light emitting element is connected between the third node and a line which transfers a second power supply voltage. In embodiments, the first capacitor may store a voltage difference between the data voltage and the initialization voltage, and the second capacitor may store a threshold voltage of the first transistor. In embodiments, in a compensation period, the third transistor may apply the reference voltage to the first node, the fourth transistor may apply the initialization voltage to the third node, the sixth transistor may diode-connect the first transistor by connecting the fourth node to the second node, and the second capacitor may store a threshold voltage of the first transistor in a diode connection manner. In embodiments, the initialization voltage may be higher than the reference voltage. In embodiments, in the compensation period, a negative gate-source voltage may be applied to the first transistor, and the threshold voltage of the first transistor may be shifted in a positive direction. In embodiments, the first gate of the first transistor may be a top gate located above an active region, and the second gate of the first transistor may be a bottom gate located under the active region. In embodiments, the first gate of the first transistor may be a bottom gate located under an active region, and the second gate of the first transisto