US-12626651-B2 - Display device and electronic device

US12626651B2US 12626651 B2US12626651 B2US 12626651B2US-12626651-B2

Abstract

A display panel of a display device includes pixels connected to data lines, a timing controller generating image data, a data driver generating data signals based on the image data and outputting the data signals through an output terminal of the data driver, and a data distributor selectively connecting the output terminal of the data driver to the data lines of the display panel based on an enable control signal. The timing controller may periodically vary a data rate based on which the image data is transmitted to the data driver and may periodically vary an output time point of the enable control signal based on the data rate.

Inventors

Soo Yeon Kim
Min Woo Kim
Chong Guk LEE
Yong Sik Hwang

Assignees

SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20241223
Priority Date: 20240701

Claims (17)

1 . A display device comprising: a display panel including pixels connected to data lines; a timing controller generating image data; a data driver generating data signals based on the image data and outputting the data signals through an output terminal of the data driver; and a data distributor selectively connecting the output terminal of the data driver to the data lines of the display panel based on an enable control signal, wherein the timing controller periodically varies a data rate based on which the image data is transmitted to the data driver and periodically varies an output time of the enable control signal based on the data rate, wherein the timing controller generates the enable control signal based on an internal clock signal, and compensates for the enable control signal based on the data rate, and wherein the timing controller compensates a period of the enable control signal in proportion to a data rate difference and a frame protocol value, the frame protocol value is a set value for a horizontal period that is a time unit in which a data signal is output from the data driver, and is included in a protocol between the timing controller and the data driver, and the data rate difference is a difference between a data rate of a previous frame and a data rate of a current frame.
2 . The display device of claim 1 , wherein the timing controller includes a spread spectrum clock generator that generates a clock signal, the data rate corresponds to a frequency of the clock signal, and the data driver outputs the data signals at a time point set based on the clock signal.
3 . The display device of claim 2 , wherein the timing controller outputs the enable control signal while each data signal is output from the data driver.
4 . The display device of claim 1 , wherein the output time of the enable control signal is varied in proportion to the data rate.
5 . The display device of claim 4 , wherein the period of the enable control signal varies inversely proportional to the data rate.
6 . The display device of claim 1 , wherein the data distributor includes a transistor connecting the output terminal of the data driver to one of the data lines, the transistor is turned on in response to the enable control signal having a first level and turned off in response to the enable control signal having a second level, and a pulse width of the enable control signal having the first level does not change, and a time period during which the enable control signal has the second level varies based on the data rate.
7 . The display device of claim 1 , wherein the timing controller compensates for the period of the enable control signal using a lookup table, and the lookup table includes a compensation value according to the data rate.
8 . The display device of claim 1 , wherein the data rate varies stepwise within a range of about ±15% with respect to a reference data rate.
9 . The display device of claim 1 , wherein the timing controller varies the data rate and the output time of the enable control signal at least once every frame.
10 . The display device of claim 9 , wherein the timing controller varies the data rate and the output time of the enable control signal for each frame.
11 . The display device of claim 10 , wherein the timing controller increases the data rate stepwise from a minimum data rate to a maximum data rate or decreases the data rate stepwise from the maximum data rate to the minimum data rate, over a certain period of time.
12 . The display device of claim 1 , wherein a refresh rate of the display panel is not variable.
13 . The display device of claim 1 , wherein the timing controller and the data driver are connected to each other through a first interface including at least one of a mobile industry processor interface (MIPI) or an Ultra path interconnect (UPI), and the timing controller provides the enable control signal to the data distributor through a general purpose input/output (GPIO) different from the first interface.
14 . An electronic device comprising: a display panel; a data driver; a demultiplexer connected between the data driver and the display panel; and a processor providing data to the data driver through a first interface and controlling an operation of the demultiplexer by providing a control signal, wherein the processor adjusts an output time of the control signal based on a data rate based on which the data is transmitted to the data driver, wherein the processor generates the control signal based on an internal clock signal, and compensates for the control signal based on the data rate, wherein the processor compensates a period of the control signal in proportion to a data rate difference and a frame protocol value, the frame protocol value is a set value for a horizontal period that is a time unit in which a data signal is output from the data driver, and is included in a protocol between the processor and the data driver, and the data rate difference is a difference between a data rate of a previous frame and a data rate of a current frame.
15 . The electronic device of claim 14 , wherein the first interface includes at least one of a mobile industry processor interface (MIPI) or an ultra path interconnect (UPI), and the processor outputs the control signal through a general purpose input/output (GPIO).
16 . The electronic device of claim 14 , wherein the output time of the control signal is varied in proportion to the data rate.
17 . The electronic device of claim 16 , wherein as the data rate increases, an output time of a data signal output from the data driver to the demultiplexer becomes earlier, and the processor adjusts the output time of the control signal to match the output time of the data signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0086313 filed in the Korean Intellectual Property Office on Jul. 1, 2024, the entire contents of which are incorporated herein by reference. BACKGROUND 1. Field An embodiment of the present disclosure relates to a display device and an electronic device. 2. Description of the Related Art With the advancement of technology, the amount of data that various electronic devices must process has rapidly increased, and as a result, the operation speed of these electronic devices is accelerated. In order to process data at high speed, electronic devices typically generate high-frequency clock signals and perform specified operations based on the generated clock signals. However, the regularly generated high-frequency clock signals cause electromagnetic interference (hereinafter referred to as “EMI”). In order to reduce such EMI, a spread spectrum clock generation method is used, which decreases the power density of each frequency of the output signal. A spread spectrum clock generator (SSCG) may reduce EMI by spreading the spectrum of the output signal frequency. SUMMARY OF THE INVENTION The present disclosure is to provide a display device and an electronic device that may improve display quality. Features of the present disclosure are not limited to the features mentioned above, and other technical features that are not mentioned may be clearly understood to a person of an ordinary skill in the art using the following description. According to an embodiment of the present disclosure, a display device includes a display panel including pixels connected to data lines, a timing controller generating image data, a data driver that generates data signals based on the image data and outputs the data signals through an output terminal of the data driver, and a data distributor selectively connecting the output terminal of the data driver to the data lines of the display panel based on an enable control signal. The timing controller may periodically vary a data rate based on which the image data is transmitted to the data driver and may periodically vary an output time of the enable control signal based on the data rate. The timing controller may include a spread spectrum clock generator that generates a clock signal, the data rate may correspond to a frequency of the clock signal, and the data driver outputs the data signals at a time point set based on the clock signal. The timing controller may output the enable control signal while each data signal is output from the data driver. The output time of the enable control signal may be varied in proportion to the data rate. A period of the enable control signal may vary inversely proportional to the data rate. The data distributor may include a transistor connecting the output terminal of the data driver to one of the data lines, the transistor may be turned on in response to the enable control signal having a first level and may be turned off in response to the enable control signal having a second level, and a pulse width of the enable control signal having the first level may not change, and a time period during which the enable control signal has the second level may vary based on the data rate. The timing controller may generate the enable control signal based on an internal clock signal, and may compensate for the enable control signal based on the data rate. The timing controller may compensate a period of the enable control signal in proportion to a data rate difference and a frame protocol value, the frame protocol value may be a set value for a horizontal period that is a time unit in which a data signal is output from the data driver, and may be included in a protocol between the timing controller and the data driver, and the data rate difference may be a difference between a data rate of a previous frame and a data rate of a current frame. The timing controller may compensate for a period of the enable control signal using a lookup table, and the lookup table may include a compensation value according to the data rate. The data rate may vary stepwise within a range of about ±15% with respect to a reference data rate. The timing controller may vary the data rate and the output time of the enable control signal at least once every frame. The timing controller may vary the data rate and the output time of the enable control signal for each frame. The timing controller may increase the data rate stepwise from a minimum data rate to a maximum data rate or may decrease the data rate stepwise from the maximum data rate to the minimum data rate, over a certain period of time. A refresh rate of the display panel may not be variable. The timing controller and the data driver may be connected to each other through a first interface including at least one of a mobile industry processor interface (MIPI) or an Ultra path interconnect (UPI), and