US-12626652-B2 - Gate driver and display apparatus including the same

US12626652B2US 12626652 B2US12626652 B2US 12626652B2US-12626652-B2

Abstract

A gate driver includes a plurality of stages. A stage of the stages includes a pull-up circuit which applies a high voltage to an output node which outputs a gate signal, a pull-down circuit which applies a low voltage lower than the high voltage to the output node, a gate signal control circuit which controls the pull-up circuit and the pull-down circuit, and a stabilization transistor connected to the pull-down circuit. The stabilization transistor is turned off when the gate signal has the low voltage.

Inventors

Hyungjin Song
NACKHYEON KEUM
Kwangsae Lee

Assignees

SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20250125
Priority Date: 20240409

Claims (14)

1 . A display apparatus comprising: a display panel including a pixel; a gate driver which outputs a gate signal to the display panel; and a data driver which applies a data voltage to the display panel, wherein the gate driver includes a plurality of stages, wherein a stage of the stages includes: a pull-up circuit which applies a high voltage to an output node which outputs the gate signal; a pull-down circuit which applies a low voltage lower than the high voltage to the output node; a gate signal control circuit which controls the pull-up circuit and the pull-down circuit; and a stabilization transistor connected to the pull-down circuit, wherein the pixel emits light based on the data voltage of a current frame during a first frame and emits light based on the data voltage of a previous frame during a second frame, wherein the stabilization transistor is turned off during a self-scan period included in the second frame and a control electrode of the stabilization transistor receives a power voltage that has a first voltage in an address period included in the first frame and a second voltage in the self-scan period, wherein the second voltage is lower than the low voltage, and wherein the gate signal control circuit includes: a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node; a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node; a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node; a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node.
2 . The display apparatus of claim 1 , wherein the stabilization transistor is an N-type transistor.
3 . The display apparatus of claim 1 , wherein the stabilization transistor includes a control electrode which receives a power voltage, a first electrode connected to the gate signal control circuit and a second electrode connected to the pull-down circuit.
4 . The display apparatus of claim 1 , wherein an absolute value of the second voltage is about twice an absolute value of the low voltage.
5 . The display apparatus of claim 1 , wherein the pull-up circuit includes a fifth transistor including a control electrode connected to the second node, a first electrode which receives the high voltage and a second electrode connected to the output node, and wherein the pull-down circuit includes a sixth transistor including a control electrode connected to the fourth node, a first electrode which receives the low voltage and a second electrode connected to the output node.
6 . The display apparatus of claim 5 , wherein the stabilization transistor includes a control electrode which receives a power voltage, a first electrode connected to the third node and a second electrode connected to the fourth node.
7 . The display apparatus of claim 1 , wherein the first electrode of the first transistor receives the vertical start signal.
8 . A display apparatus comprising: a display panel including a pixel; a gate driver which outputs a gate signal to the display panel; and a data driver which applies a data voltage to the display panel, wherein the gate driver includes a plurality of stages, wherein a stage of the stages includes: a pull-up circuit which applies a high voltage to an output node which outputs the gate signal; a pull-down circuit which applies a low voltage lower than the high voltage to the output node; a gate signal control circuit which controls the pull-up circuit and the pull-down circuit; and a stabilization transistor connected to the pull-down circuit, wherein the stabilization transistor is turned off during a blank period in which the data voltage is not applied to the pixel, and a control electrode of the stabilization transistor receives a power voltage that has a first voltage in an address period included in the first frame and a second voltage in the self-scan period, wherein the second voltage is lower than the low voltage, and wherein the gate signal control circuit includes: a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node; a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node; a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node; a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node.
9 . The display apparatus of claim 8 , wherein the stabilization transistor is an N-type transistor.
10 . The display apparatus of claim 8 , wherein the stabilization transistor includes a control electrode which receives a power voltage, a first electrode connected to the gate signal control circuit and a second electrode connected to the pull-down circuit.
11 . A gate driver comprising: a plurality of stages, wherein a stage of the stages includes, a pull-up circuit which applies a high voltage to an output node which outputs a gate signal; a pull-down circuit which applies a low voltage lower than the high voltage to the output node; a gate signal control circuit which controls the pull-up circuit and the pull-down circuit; and a stabilization transistor connected to the pull-down circuit, wherein the stabilization transistor is turned off when the gate signal has the low voltage, and a control electrode of the stabilization transistor receives a power voltage that has a first voltage in an address period included in the first frame and a second voltage in the self-scan period, wherein the second voltage is lower than the low voltage, and wherein the gate signal control circuit includes: a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node; a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node; a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node; a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node.
12 . The gate driver of claim 11 , wherein the stabilization transistor is an N-type transistor.
13 . The gate driver of claim 11 , wherein the stabilization transistor includes a control electrode which receives a power voltage, a first electrode connected to the gate signal control circuit and a second electrode connected to the pull-down circuit.
14 . An electronic apparatus comprising: a display panel including a pixel; a gate driver which outputs a gate signal to the display panel; a data driver which applies a data voltage to the display panel; a driving controller which controls the gate driver and the data driver based on an input control signal; and a processor which outputs the input control signal, wherein the gate driver includes a plurality of stages, wherein a stage of the stages includes: a pull-up circuit which applies a high voltage to an output node which outputs the gate signal; a pull-down circuit which applies a low voltage lower than the high voltage to the output node; a gate signal control circuit which controls the pull-up circuit and the pull-down circuit; and a stabilization transistor connected to the pull-down circuit, wherein the pixel emits light based on the data voltage of a current frame during a first frame and emits light based on the data voltage of a previous frame during a second frame, wherein the stabilization transistor is turned off during a self-scan period included in the second frame, and a control electrode of the stabilization transistor receives a power voltage that has a first voltage in an address period included in the first frame and a second voltage in the self-scan period, wherein the second voltage is lower than the low voltage, and wherein the gate signal control circuit includes: a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node; a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node; a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node; a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node.

Description

This application claims priority to Korean Patent Application No. 10-2024-0047848, filed on Apr. 9, 2024, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference. BACKGROUND 1. Field Embodiments of the invention relate to a gate driver and a display apparatus including the gate driver. More particularly, embodiments of the invention relate to a gate driver with improved output stability and a display apparatus including the gate driver. 2. Description of the Related Art Generally, a display apparatus includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines and a plurality of pixels. The display panel driver includes a gate driver for providing a gate signal to the gate lines, a data driver for providing a data voltage to the data lines and a driving controller for controlling the gate driver and the data driver. SUMMARY In a display apparatus, an output stability of gate signal may be deteriorated by a leakage current flowing in a gate driver. Embodiments of the invention provide a gate driver with improved output stability. Embodiments of the invention also provide a display apparatus including the gate driver. According to embodiments, a display apparatus includes a display panel including a pixel, a gate driver which output a gate signal to the display panel and a data driver which applies a data voltage to the display panel. In such embodiments, the gate driver includes a plurality of stages. In such embodiments, a stage of the stages includes a pull-up circuit which apply a high voltage to an output node which outputs the gate signal, a pull-down circuit which applies a low voltage lower than the high voltage to the output node, a gate signal control circuit which controls the pull-up circuit and the pull-down circuit, and a stabilization transistor connected to the pull-down circuit. In such embodiments, the pixel emits light based on the data voltage of a current frame during a first frame and emits light based on the data voltage of a previous frame during a second frame. In such embodiments, the stabilization transistor is turned off during a self-scan period included in the second frame. In an embodiment, the stabilization transistor may be an N-type transistor. In an embodiment, the stabilization transistor may include a control electrode which receives a power voltage, a first electrode connected to the gate signal control circuit and a second electrode connected to the pull-down circuit. In an embodiment, wherein the power voltage may have a first voltage in an address period included in the first frame. In such an embodiment, the power voltage may have a second voltage lower than the first voltage in the self-scan period. In an embodiment, the second voltage may be lower than the low voltage. In an embodiment, an absolute value of the second voltage may be about twice an absolute value of the low voltage. In an embodiment, the gate signal control circuit may include a first transistor including a control electrode which receives a clock signal, a first electrode which receives a previous stage gate signal or a vertical start signal and a second electrode connected to a first node, a second transistor including a control electrode connected to the first node, a first electrode which receives the high voltage and a second electrode connected to a second node, a third transistor including a control electrode which receives the low voltage, a first electrode connected to the first node and a second electrode connected to a third node, a fourth transistor including a control electrode connected to a fourth node, a first electrode which receives the low voltage and a second electrode connected to the second node. In an embodiment, the pull-up circuit may include a fifth transistor including a control electrode connected to the second node, a first electrode which receives the high voltage and a second electrode connected to the output node. In such an embodiment, the pull-down circuit may include a sixth transistor including a control electrode connected to the fourth node, a first electrode which receives the low voltage and a second electrode connected to the output node. In an embodiment, the stabilization transistor may include a control electrode which receives a power voltage, a first electrode connected to the third node and a second electrode connected to the fourth node. In an embodiment, the first electrode of the first transistor may receive the vertical start signal. According to embodiments, a display apparatus may comprise a display panel including a pixel, a gate driver which outputs a gate signal to the display panel, a data driver which applies a data voltage to the display panel. In such embodiments, the gate driver may include a plurality of stages. In such embodiments, a stage of the stages may include a pull-up circuit which