US-12626654-B2 - Display device and gate drive unit comprising frequency-division control module

Abstract

A gate drive unit and a display device in which a plurality of cascaded gate drive circuits are electrically connected to a frequency-division control line configured to transmit a frequency-division control signal, so that a frequency-division control module in each gate drive circuit controls signal transmission between a first power supply terminal and a first node or a second node according to the frequency-division control signal, thereby controlling level states of gate control signals outputted by a first output module and a second output module.

Inventors

• Huanxi Zhang

Assignees

• WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.

Dates

Publication Date

20260512

Application Date

20231229

Priority Date

20231226

Claims (16)

1. 1 . A gate drive unit, comprising a frequency-division control line and a plurality of cascaded gate drive circuits, the frequency-division control line being configured to transmit one or more frequency-division control signals to the plurality of gate drive circuits, each of the gate drive circuits comprising: a first control module electrically connected to a first node of a current-stage gate drive circuit of the plurality of gate drive circuits and configured to control signal transmission between the first node and one of a first power supply terminal and a second power supply terminal according to a corresponding first clock signal and one of a first gate control signal outputted by a previous-stage gate drive circuit of the plurality of gate drive circuits and a start signal; a first output module electrically connected to at least the first node of the current-stage gate drive circuit and configured to control an electrical connection between a third power supply terminal and a first output terminal of the current-stage gate drive circuit according to a potential of the first node, wherein the first output terminal outputs the first gate control signal of the current-stage gate drive circuit; a second output module electrically connected to a second node of the current-stage gate drive circuit and a third node of the current-stage gate drive circuit, and configured to output a second gate control signal of the current-stage gate drive circuit according to a potential of the second node and a potential of the third node; and a frequency-division control module electrically connected to the first node of the current-stage gate drive circuit and configured to control signal transmission between the first power supply terminal and the first node or the second node according to the frequency-division control signal; wherein the first control module comprises: a first transistor having a first control terminal and a second control terminal configured to receive one of the first gate control signal outputted by the previous-stage gate drive circuit and the start signal, and an input terminal electrically connected to the first power supply terminal; a second transistor having a control terminal electrically connected to the first control terminal of the first transistor, an input terminal electrically connected to the second power supply terminal, and an output terminal electrically connected to an output terminal of the first transistor; and a third transistor having a control terminal configured to receive the corresponding first clock signal, an input terminal electrically connected to the output terminal of the first transistor, and an output terminal electrically connected to the first node; wherein the frequency-division control module is electrically connected to the first transistor or the third transistor.
2. 2 . The gate drive unit according to claim 1 , wherein the frequency-division control module comprises: a frequency-division transistor having a control terminal configured to receive the frequency-division control signal, an input terminal electrically connected to the output terminal of the third transistor, and an output terminal electrically connected to the first node.
3. 3 . The gate drive unit according to claim 1 , wherein the frequency-division control module comprises: a frequency-division transistor having a control terminal configured to receive the frequency-division control signal, an input terminal configured to receive the corresponding first clock signal, and an output terminal electrically connected to the control terminal of the third transistor.
4. 4 . The gate drive unit according to claim 1 , wherein the frequency-division control module comprises: a frequency-division transistor having a control terminal configured to receive the frequency-division control signal, an input terminal configured to receive the start signal or the first gate control signal outputted by the previous-stage gate drive circuit, and an output terminal electrically connected to the first control terminal of the first transistor.
5. 5 . The gate drive unit according to claim 1 , wherein the first output module comprises a first output transistor and a second output transistor, a first control terminal and a second control terminal of the first output transistor and a control terminal of the second output transistor being electrically connected to the first node, an input terminal of the first output transistor being electrically connected to the third power supply terminal, an input terminal of the second output transistor being electrically connected to a fourth power supply terminal, and an output terminal of the second output transistor and an output terminal of the first output transistor being electrically connected to the first output terminal of the current-stage gate drive circuit; the second output module comprises a third output transistor, a fourth output transistor and a storage capacitor, a control terminal of the third output transistor being electrically connected to the second node, an input terminal of the third output transistor being configured to receive a corresponding second clock signal, a control terminal of the fourth output transistor being electrically connected to the third node, an input terminal of the fourth output transistor being electrically connected to the second power supply terminal; an output terminal of the fourth output transistor and an output terminal of the third output transistor being electrically connected to a second output terminal of the current-stage gate drive circuit; a first terminal of the storage capacitor being electrically connected to the control terminal of the third output transistor, and a second terminal of the storage capacitor being electrically connected to the second output terminal of the current-stage gate drive circuit.
6. 6 . The gate drive unit according to claim 1 , wherein the second node comprises a first sub-node and a second sub-node, and the frequency-division control signals comprise a first frequency-division control signal and a second frequency-division control signal; the frequency-division control module comprises: a first frequency-division control module electrically connected to the first node and the first sub-node and configured to control signal transmission between the first power supply terminal and the first sub-node according to the first frequency-division control signal; and a second frequency-division control module electrically connected to the first node and the second sub-node and configured to control signal transmission between the first power supply terminal and the second sub-node according to the second frequency-division control signal; wherein the first output module is electrically connected to the first sub-node, and the first output module is configured to output the first gate control signal of the current-stage gate drive circuit according to the potential of the first node and a potential of the first sub-node; the second output module is electrically connected to the second sub-node, and the second output module is configured to output the second gate control signal of the current-stage gate drive circuit according to a potential of the second sub-node and the potential of the third node.
7. 7 . The gate drive unit according to claim 6 , wherein the first frequency-division control module comprises a first frequency-division transistor, a second frequency-division transistor, and a first capacitor, a control terminal of the first frequency-division transistor being electrically connected to the third node of the current-stage gate drive circuit, and an input terminal of the first frequency-division transistor being configured to receive the first frequency-division control signal; a control terminal of the second frequency-division transistor being electrically connected to an output terminal of the first frequency-division transistor, an input terminal of the second frequency-division transistor being electrically connected to the first node, and an output terminal of the second frequency-division transistor being electrically connected to the first sub-node; a first terminal of the first capacitor being electrically connected to the control terminal of the second frequency-division transistor, and a second terminal of the first capacitor being electrically connected to the first sub-node; the second frequency-division control module comprises a third frequency-division transistor, a fourth frequency-division transistor, and a second capacitor, a control terminal of the third frequency-division transistor being electrically connected to the third node of the current-stage gate drive circuit, and an input terminal of the third frequency-division transistor being configured to receive the second frequency-division control signal; a control terminal of the fourth frequency-division transistor being electrically connected to an output terminal of the third frequency-division transistor, an input terminal of the fourth frequency-division transistor being electrically connected to the first node, and an output terminal of the fourth frequency-division transistor being electrically connected to the second sub-node; a first terminal of the second capacitor being electrically connected to the control terminal of the fourth frequency-division transistor, and a second terminal of the second capacitor being electrically connected to the second sub-node.
8. 8 . The gate drive unit according to claim 7 , wherein the first output module comprises a first output transistor and a second output transistor, a first control terminal and a second control terminal of the first output transistor being electrically connected to the first node, an input terminal of the first output transistor being electrically connected to the third power supply terminal, a control terminal of the second output transistor being electrically connected to the first sub-node, an input terminal of the second output transistor being electrically connected to a fourth power supply terminal, and an output terminal of the second output transistor and an output terminal of the first output transistor being electrically connected to the first output terminal of the current-stage gate drive circuit; the second output module comprises a third output transistor, a fourth output transistor and a storage capacitor, a control terminal of the third output transistor being electrically connected to the second sub-node, an input terminal of the third output transistor being configured to receive a corresponding second clock signal, a control terminal of the fourth output transistor being electrically connected to the third node, an input terminal of the fourth output transistor being electrically connected to the second power supply terminal, and an output terminal of the fourth output transistor and an output terminal of the third output transistor being electrically connected to a second output terminal of the current-stage gate drive circuit; a first terminal of the storage capacitor being electrically connected to the control terminal of the third output transistor, and a second terminal of the storage capacitor being electrically connected to the second output terminal of the current-stage gate drive circuit.
9. 9 . The gate drive unit according to claim 1 , wherein the first control module further comprises a fourth transistor, a fifth transistor and a sixth transistor, a first control terminal and a second control terminal of the fourth transistor being configured to receive the corresponding first clock signal, an output terminal of the fourth transistor being electrically connected to the first node; a control terminal of the fifth transistor, a first control terminal and a second control terminal of the sixth transistor being electrically connected to the third node, an input terminal of the fifth transistor being electrically connected to the second power supply terminal, an output terminal of the fifth transistor being electrically connected to an input terminal of the fourth transistor, an input terminal of the sixth transistor being electrically connected to the third power supply terminal, and an output terminal of the sixth transistor being electrically connected to the first node; the gate drive unit further comprises a seventh transistor and an eighth transistor, a first control terminal and a second control terminal of the seventh transistor being electrically connected to the first node, an input terminal of the seventh transistor being electrically connected to the first power supply terminal, an output terminal of the seventh transistor being electrically connected to the third node, a control terminal of the eighth transistor being electrically connected to the first node, an input terminal of the eighth transistor being electrically connected to the second power supply terminal, and an output terminal of the eighth transistor being electrically connected to the third node.
10. 10 . The gate drive unit according to claim 5 , wherein the gate drive circuit further comprises: a first switching transistor having an input terminal electrically connected to the first node; a second switching transistor having an input terminal electrically connected to an output terminal of the first switching transistor, and an output terminal electrically connected to the second node; and a third capacitor having a first terminal electrically connected to a control terminal of the first switching transistor and a second terminal electrically connected to the output terminal of the first switching transistor; wherein the control terminal of the first switching transistor of an nth-stage gate drive circuit of the plurality of gate drive circuits is configured to receive the first gate control signal outputted by an (n−10)th-stage gate drive circuit of the plurality of gate drive circuits, and the control terminal of the second switching transistor of the nth-stage gate drive circuit is configured to receive the first gate control signal outputted by an (n−2)th-stage gate drive circuit of the plurality of gate drive circuits.
11. 11 . The gate drive unit according to claim 8 , wherein the gate drive circuit further comprises: a ninth transistor having a first control terminal and a second control terminal configured to receive the corresponding first clock signal, and an output terminal electrically connected to the first sub-node; a tenth transistor having a control terminal electrically connected to the third node of the current-stage gate drive circuit, an input terminal electrically connected to the second power supply terminal, and an output terminal electrically connected to an input terminal of the ninth transistor; an eleventh transistor having a control terminal electrically connected to the third node of the previous-stage gate drive circuit, an input terminal electrically connected to the output terminal of the third frequency-division transistor, and an output terminal electrically connected to the second sub-node; a twelfth transistor having a first control terminal and a second control terminal configured to receive the corresponding first clock signal, an output terminal electrically connected to the input terminal of the eleventh transistor; a thirteenth transistor having a control terminal electrically connected to the third node of the current-stage gate drive circuit, an input terminal electrically connected to the second power supply terminal, and an output terminal electrically connected to an input terminal of the twelfth transistor.
12. 12 . A display device, comprising: a gate drive unit and a display panel; wherein the gate drive unit comprising a frequency-division control line and a plurality of cascaded gate drive circuits, the frequency-division control line being configured to transmit one or more frequency-division control signal to the plurality of gate drive circuits, each of the gate drive circuits comprising: a first control module electrically connected to a first node of a current-stage gate drive circuit of the plurality of gate drive circuits and configured to control signal transmission between the first node and one of a first power supply terminal and a second power supply terminal according to a corresponding first clock signal and one of a first gate control signal outputted by a previous-stage gate drive circuit of the plurality of gate drive circuits and a start signal; a first output module electrically connected to at least the first node of the current-stage gate drive circuit and configured to control an electrical connection between a third power supply terminal and a first output terminal of the current-stage gate drive circuit according to a potential of the first node, wherein the first output terminal outputs the first gate control signal of the current-stage gate drive circuit; a second output module electrically connected to a second node of the current-stage gate drive circuit and a third node of the current-stage gate drive circuit, and configured to output a second gate control signal of the current-stage gate drive circuit according to a potential of the second node and a potential of the third node; and a frequency-division control module electrically connected to the first node of the current-stage gate drive circuit and configured to control signal transmission between the first power supply terminal and the first node or the second node according to the frequency-division control signal; wherein the display panel comprising a plurality of sub-pixels, each of the sub-pixels comprising a light-emitting device and a pixel drive circuit configured to drive the light-emitting device to emit light, the pixel drive circuit comprising at least a drive transistor, a data transistor and a compensation transistor; the drive transistor being configured to drive the light-emitting device to emit light according to a corresponding data signal, an input terminal of the compensation transistor being electrically connected to an output terminal of the drive transistor, an output terminal of the compensation transistor being electrically connected to a control terminal of the drive transistor, an input terminal of the data transistor being configured to receive the corresponding data signal, and an output terminal of the data transistor being electrically connected to an input terminal of the drive transistor; wherein a number of first gate control signals generated by the plurality of gate drive circuits are outputted to control terminals of the compensation transistors of the plurality of sub-pixels, and a number of second gate control signals generated by the plurality of gate drive circuits are outputted to control terminals of the data transistors of the plurality of sub-pixels; and wherein the control terminal of the data transistor of the sub-pixel located in an nth row receives an nth-stage second gate control signal outputted by an nth-stage gate drive circuit of the plurality of gate drive circuits; the control terminal of the compensation transistor of the sub-pixel located in the nth row receives an (n+1)th-stage first gate control signal outputted by an (n+1)th-stage gate drive circuit of the plurality of gate drive circuits.
13. 13 . The display device according to claim 12 , wherein the pixel drive circuit comprises a first reset transistor having an input terminal configured to receive a first reset signal, and an output terminal electrically connected to the control terminal of the drive transistor; wherein the first gate control signals generated by the plurality of gate drive circuits are outputted to control terminals of the first reset transistors of the plurality of sub-pixels; and for each sub-pixel, the first gate control signal received at the control terminal of the first reset transistor and the first gate control signal received at the control terminal of the compensation transistor are provided by the gate drive circuits at different stages.
14. 14 . The display device according to claim 13 , wherein the control terminal of the first reset transistor of the sub-pixel located in an nth row receives an (n−3)th-stage first gate control signal outputted by an (n−3)th-stage gate drive circuit of the plurality of gate drive circuits; the control terminal of the compensation transistor of the sub-pixel located in the nth row receives an (n+1)th-stage first gate control signal outputted by an (n+1)th-stage gate drive circuit of the plurality of gate drive circuits.
15. 15 . The display device according to claim 12 , wherein each of the pixel drive circuits further comprises: a second reset transistor having a control terminal configured to receive a reset control signal, an input terminal configured to receive a second reset signal, and an output terminal electrically connected to an anode of the light-emitting device; a first light-emitting control transistor having a control terminal configured to receive a light-emitting control signal, an input terminal and an output terminal electrically connected between the first power supply terminal and the input terminal of the drive transistor; a second light-emitting control transistor having a control terminal configured to receive the light-emitting control signal, an input terminal and an output terminal electrically connected between the light-emitting device and the output terminal of the drive transistor; and a fourth capacitor connected in series between the first power supply terminal and the control terminal of the drive transistor.
16. 16 . The display device according to claim 15 , wherein each of the pixel drive circuits further comprises: a third reset transistor having a control terminal configured to receive the reset control signal, an input terminal configured to receive a third reset signal, and an output terminal electrically connected to the input terminal of the drive transistor; and a fifth capacitor connected in series between the control terminal of the drive transistor and the control terminal of the data transistor.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a US national phase application based upon an International Application No. PCT/CN2023/143365, filed on Dec. 29, 2023, and entitled “GATE DRIVE UNIT AND DISPLAY DEVICE”, which claims priority to Chinese Patent Application No. 202311814730.0, filed on Dec. 26, 2023, and entitled “GATE DRIVE UNIT AND DISPLAY DEVICE”, the contents of which are incorporated herein by reference in their entireties. TECHNICAL FIELD The present disclosure relates to the field of display technologies, and more particularly, to a gate drive unit and a display device. BACKGROUND The adoption of a variable refresh rate design can reduce power consumption of a display panel. However, in some use scenarios, the display panel corresponds to different display regions with different display screen contents. If different display regions are still driven to display different display screens by employing a same refresh rate, the region(s) for displaying the static screen(s) and the region(s) for displaying the dynamic screen(s) are driven by employing the same refresh rate, which may cause resource waste. SUMMARY An embodiment of the present disclosure provides a gate drive circuit and a display device, which may realize region-partition frequency-division driving. An embodiment of the present disclosure provides a gate drive unit including a frequency-division control line and a plurality of cascaded gate drive circuits, the frequency-division control line configured to transmit a frequency-division control signal to the plurality of gate drive circuits. Each of the gate drive circuits includes a first control module, a first output module, a second output module, and a frequency-division control module. The first control module is electrically connected to a first node of a current-stage gate drive circuit, and the first control module is configured to control signal transmission between the first node and one of a first power supply terminal and a second power supply terminal according to a corresponding first clock signal and one of a start signal and a first gate control signal outputted by a previous-stage gate drive circuit. The first output module is electrically connected to at least the first node of the current-stage gate drive circuit, the first output module is configured to control an electrical connection between a third power supply terminal and a first output terminal of the current-stage gate drive circuit according to a potential of the first node, and the first output terminal outputs a first gate control signal of the current-stage gate drive circuit. The second output module is electrically connected to a second node of the current-stage gate drive circuit and a third node of the current-stage gate drive circuit, and the second output module is configured to output a second gate control signal of the current-stage gate drive circuit according to a potential of the second node and a potential of the third node. The frequency-division control module is electrically connected to the first node of the current-stage gate drive circuit, and the frequency-division control module is configured to control signal transmission between the first power supply terminal and the first node or the second node according to the frequency-division control signal. An embodiment of the present disclosure further provides a display device including the gate drive unit as described above and a display panel. The display panel includes a plurality of sub-pixels, each sub-pixel including a light-emitting device and a pixel drive circuit for driving the light-emitting device to emit light, the pixel drive circuit including at least a drive transistor, a data transistor and a compensation transistor. The drive transistor is configured to drive the light-emitting device to emit light according to a corresponding data signal, an input terminal of the compensation transistor is electrically connected to an output terminal of the drive transistor, an output terminal of the compensation transistor is electrically connected to a control terminal of the drive transistor, an input terminal of the data transistor is configured to receive the corresponding data signal, and an output terminal of the data transistor is electrically connected to an input terminal of the drive transistor. Wherein the first gate control signals generated by the plurality of gate drive circuits are outputted to the control terminals of the compensation transistors of the plurality of sub-pixels, and the second gate control signals generated by the plurality of gate drive circuits are outputted to control terminals of the data transistors of the plurality of sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1B are schematic structural diagrams of a gate drive unit according to an embodiment of the present disclosure; FIGS. 2A-2D are circuit diagrams of a gate drive circuit according to an embodiment of the present dis