US-12626658-B2 - Display substrate and display panel for improving uniformity of image quality and brightness

Abstract

The present disclosure relates to the technical field of display. Provided are a display substrate and a display panel. The display substrate comprises a plurality of sub-pixels, wherein each sub-pixel comprises a pixel driving circuit and a light emitting device, which are electrically connected to each other; the pixel driving circuit comprises a driving module, a first reset module, a second reset module, an input module, a first light-emission control module, a second light-emission control module, and a compensation module; the pixel driving circuit comprises a plurality of transistors, and each transistor comprises an active portion. The display substrate further comprises a plurality of conductive patterns, wherein orthographic projections of active portions of all the transistors in at least one of the sub-pixels on a base are all located within orthographic projections of the conductive patterns on the base. The display substrate is used for preparing a display panel.

Inventors

• Mengmeng Du
• Yao Huang
• Jun Yan
• Ansu LEE

Assignees

• CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
• BOE TECHNOLOGY GROUP CO., LTD.
• Beijing Boe Technology Development Co., Ltd.

Dates

Publication Date

20260512

Application Date

20240117

Priority Date

20230426

Claims (16)

1. 1 . A display substrate, comprising: a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein each of the plurality of sub-pixels comprises a pixel driving circuit and a light emitting device that are electrically connected, and the pixel driving circuit comprises: a driving module electrically connected to a first node, a second node and a third node respectively, wherein the third node is electrically connected to an anode of the light emitting device, and the driving module is configured to conduct a path between the second node and the anode under a control of a voltage of the first node, and generate a current in the path for driving the light emitting device to emit light; a first reset module and a second reset module, wherein the first reset module is electrically connected to the third node, a first reset signal line and a second initialization signal line respectively, and is configured to initialize a voltage of the anode under a control of a signal transmitted by the first reset signal line; and the second reset module is electrically connected to the first node, a fourth node, a second reset signal line and a first initialization signal line respectively, and is configured to initialize a voltage of the first node and a voltage of the fourth node under a control of a signal transmitted by the second reset signal line; an input module electrically connected to a scanning signal line, a data signal line and a fifth node respectively, and configured to input a data signal transmitted by the data signal line to the fifth node under a control of a signal input by the scanning signal line; a first light emitting control module and a second light emitting control module, wherein the first light emitting control module is electrically connected to a first light emitting control signal line, a positive power signal line and the second node respectively, and is configured to input a signal transmitted by the positive power signal line to the second node under a control of a signal transmitted by the first light emitting control signal line; and the second light emitting control module is electrically connected to the first node, the fifth node and a second light emitting control signal line respectively, and is configured to transmit a signal of the fifth node to the first node under a control of a signal transmitted by the second light emitting control signal line; and a compensation module electrically connected to the third node, the fourth node and the fifth node respectively, and configured to compensate a threshold voltage of the driving module, wherein the pixel driving circuit comprises a plurality of transistors, and each of the plurality of transistors comprises an active portion; the display substrate further comprises a plurality of conductive patterns, a part of the plurality of conductive patterns are located on a side of the active portion of the transistor away from the substrate, and a part of the plurality of conductive patterns are located between the active portion of the transistor and the substrate, wherein orthographic projections of active portions of the plurality of transistors in at least one of the plurality of sub-pixels on the substrate are located within orthographic projections of the plurality of conductive patterns on the substrate, wherein the second reset module comprises a first transistor and a second transistor, the driving module comprises a third transistor, the input module comprises a fourth transistor, the first light emitting control module comprises a fifth transistor, the second light emitting control module comprises a sixth transistor, the first reset module comprises a seventh transistor, and the compensation module comprises a first capacitor and a second capacitor, wherein a gate of the first transistor and a gate of the second transistor are both electrically connected to the second reset signal line, a source of the first transistor is electrically connected to the first node, a drain of the first transistor is electrically connected to the fourth node, a source of the second transistor is electrically connected to the fourth node, and a drain of the second transistor is electrically connected to the first initialization signal line, wherein a gate of the third transistor is electrically connected to the first node, a source of the third transistor is electrically connected to a drain of the fifth transistor through the second node, and a drain of the third transistor is electrically connected to the anode through the third node, wherein a gate of the fourth transistor is electrically connected to the scanning signal line, a source of the fourth transistor is electrically connected to the data signal line, and a drain of the fourth transistor is electrically connected to the fifth node, wherein a gate of the fifth transistor is electrically connected to the first light emitting control signal line, a source of the fifth transistor is electrically connected to the positive power signal line, a gate of the sixth transistor is electrically connected to the second light emitting control signal line, a source of the sixth transistor is electrically connected to the first node, and a drain of the sixth transistor is electrically connected to the fifth node, wherein a gate of the seventh transistor is electrically connected to the first reset signal line, a source of the seventh transistor is electrically connected to the third node, and a drain of the seventh transistor is electrically connected to the second initialization signal line, wherein a first electrode of the first capacitor is electrically connected to a first electrode of the second capacitor, a second electrode of the first capacitor is electrically connected to the third node, and a second electrode of the second capacitor is electrically connected to the fifth node, wherein the display substrate comprises a first conductive layer, wherein the first conductive layer is located on the side of the active portion of the transistor away from the substrate, wherein the first conductive layer comprises the positive power signal line, the scanning signal line, the second light emitting control signal line, the first initialization signal line, the second reset signal line and the second initialization signal line that are sequentially arranged in a first direction and extend in a second direction, and wherein an orthographic projection of the scanning signal line on the substrate at least partially overlaps with an orthographic projection of an active portion of the fourth transistor in a same row of sub-pixels arranged in the second direction on the substrate; an orthographic projection of the second light emitting control signal line on the substrate at least partially overlaps with an orthographic projection of an active portion of the sixth transistor in the same row of sub-pixels arranged in the second direction on the substrate; an orthographic projection of the second reset signal line on the substrate at least partially overlaps with an orthographic projection of an active portion of the first transistor in the same row of sub-pixels arranged in the second direction on the substrate, and the orthographic projection of the second reset signal line on the substrate at least partially overlaps with an orthographic projection of an active portion of the second transistor in the same row of sub-pixels arranged in the second direction on the substrate, wherein the first direction intersects with the second direction.
2. 2 . The display substrate according to claim 1 , wherein the plurality of conductive patterns comprise a combination of one or more of the anode of the light emitting device, a signal line, a connection wiring, and a gate of the transistor.
3. 3 . The display substrate according to claim 1 , wherein one of the plurality of sub-pixels is located at an area defined by two adjacent data lines and two adjacent positive power signal lines, and the plurality of sub-pixels comprise a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels that are sequentially arranged in the second direction, and one of the plurality of first sub-pixels, one of the plurality of second sub-pixels and one of the plurality of third sub-pixels that are sequentially arranged in the second direction form a pixel unit, and a plurality of pixel units are arranged in an array in the first direction and the second direction; and the plurality of conductive patterns comprise a first conductive pattern, a second conductive pattern and a third conductive pattern, wherein the first conductive pattern is located on the first conductive layer, and a portion of the first conductive pattern located at a position of the first sub-pixel, a portion of the first conductive pattern located at a position of the second sub-pixel and a portion of the first conductive pattern located at a position of the third sub-pixel are not completely the same.
4. 4 . The display substrate according to claim 3 , wherein the portion of the first conductive pattern located at the position of the third sub-pixel comprises a first shielding portion, wherein an orthographic projection of the first shielding portion on the substrate at least partially overlaps with an orthographic projection of an active portion of the seventh transistor in the third sub-pixel on the substrate, and the first shielding portion is further used as a connection wiring connecting an anode of the third sub-pixel and the source of the seventh transistor.
5. 5 . The display substrate according to claim 3 , wherein the display substrate further comprises a second conductive layer, wherein the second conductive layer is located on a side of the first conductive layer away from the substrate, and a first insulating layer is arranged between the first conductive layer and the second conductive layer; and the second conductive layer comprises a plurality of data signal lines extending in the first direction, the second conductive pattern is located on the second conductive layer, the second conductive pattern comprises a plurality of second shielding portions and a plurality of third shielding portions, one of the plurality of second shielding portions and one of the plurality of third shielding portions are arranged between two adjacent data signal lines, and orthographic projections of the plurality of second shielding portions on the substrate do not overlap with orthographic projections of the plurality of third shielding portions on the substrate, wherein the orthographic projections of the active portions of the first transistor, the second transistor, the fourth transistor and the sixth transistor on the substrate all at least partially overlap with the orthographic projections of the plurality of second shielding portions on the substrate, and orthographic projections of active portions of the third transistor, the fifth transistor and the seventh transistor on the substrate all at least partially overlap with the orthographic projections of the plurality of third shielding portions on the substrate.
6. 6 . The display substrate according to claim 5 , wherein the plurality of second shielding portions are electrically connected to the positive power signal line, and the plurality of third shielding portions are electrically connected to at least one of the first initialization signal line, the second initialization signal line or a negative power signal line.
7. 7 . The display substrate according to claim 6 , wherein a portion of the plurality of third shielding portions located at the position of the first sub-pixel is electrically connected to the first initialization signal line, a portion of the plurality of third shielding portions located at the position of the second sub-pixel is electrically connected to the second initialization signal line, a portion of the plurality of third shielding portions located at the position of the third sub-pixel is electrically connected to the negative power signal line, and the negative power signal line is electrically connected to a cathode of the light emitting device.
8. 8 . The display substrate according to claim 5 , wherein the display substrate further comprises a third conductive layer, wherein the third conductive layer is located on a side of the second conductive layer away from the substrate, a second insulating layer is arranged between the second conductive layer and the third conductive layer, and the third conductive layer comprises anodes of light emitting devices in all the sub-pixels, wherein in the same pixel unit, the anode of the light emitting device in the third sub-pixel covers at least the active portion of the second transistor and the active portion of the third transistor in the first sub-pixel, and further covers at least the active portion of the sixth transistor, the active portion of the first transistor, the active portion of the second transistor and the active portion of the third transistor in the second sub-pixel, and further covers at least a partial area of the active portion of the first transistor and a partial area of the active portion of the sixth transistor in the third sub-pixel; the anode of the light emitting device in the first sub-pixel covers at least the active portion of the seventh transistor in the first sub-pixel, and the anode of the light emitting device in the second sub-pixel covers at least the active portion of the seventh transistor in the second sub-pixel.
9. 9 . The display substrate according to claim 8 , wherein in two adjacent pixel units arranged in the first direction, the anode of the first sub-pixel in one pixel unit further covers at least a partial area of the active portion of the fourth transistor and the active portion of the fifth transistor in the first sub-pixel in the other pixel unit; and the anode of the second sub-pixel in one pixel unit further covers at least the active portion of the fifth transistor in the second sub-pixel in the other pixel unit, and a partial area of the active portion of the third sub-pixel and a partial area of the active portion of the fourth transistor.
10. 10 . The display substrate according to claim 8 , wherein the third conductive pattern is located on the third conductive layer, and the third conductive pattern comprises a plurality of fourth shielding portions, wherein the plurality of fourth shielding portions cover at least the active portion of the third transistor in the third sub-pixel, and the plurality of fourth shielding portions and the anode of the light emitting device in the third sub-pixel are of an integrated structure.
11. 11 . The display substrate according to claim 1 , wherein the display substrate further comprises a fourth conductive layer and a fifth conductive layer, wherein the fourth conductive layer is located between the substrate and the fifth conductive layer, and the fifth conductive layer is located between the first conductive layer and the fourth conductive layer; the fourth conductive layer comprises the first electrode of the first capacitor and the first electrode of the second capacitor, and the first electrode of the first capacitor and the first electrode of the second capacitor are of an integrated structure; and the fifth conductive layer comprises a first light emitting control auxiliary line, a first reset auxiliary line, the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor, the second electrode of the first capacitor and the second electrode of the second capacitor, wherein the gate of the first transistor and the gate of the second transistor are of an integrated structure, the gate of the third transistor is shared with the second electrode of the first capacitor, the gate of the fifth transistor and the first light emitting control auxiliary line are of an integrated structure, the gate of the seventh transistor and the first reset auxiliary line are of an integrated structure; the first light emitting control auxiliary line is electrically connected to the first light emitting control signal line, and the first reset auxiliary line is electrically connected to the first reset signal line.
12. 12 . The display substrate according to claim 11 , wherein the display substrate further comprises a semiconductor layer, wherein the semiconductor layer is located on a side of the fifth conductive layer away from the fourth conductive layer; in an area where the sub-pixel is located, the semiconductor layer comprises a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion and a seventh portion, wherein the first portion comprises the source, the drain and the active portion of the first transistor, the second portion comprises the source, the drain and the active portion of the second transistor, the third portion comprises the source, the drain and the active portion of the third transistor, the fourth portion comprises the source, the drain and the active portion of the fourth transistor, and the fifth portion comprises the source, the drain and the active portion of the fifth transistor, the sixth portion comprises the source, the drain and the active portion of the sixth transistor, and the seventh portion comprises the source, the drain and the active portion of the seventh transistor, wherein the fourth portion, the sixth portion and the first portion all extend in the first direction and are sequentially connected, the second portion is located on a side of the first portion close to the third portion and is connected to the first portion, and the fifth portion, the third portion and the seventh portion all extend in the first direction and are sequentially connected; and an area of the semiconductor layer overlapping with an orthographic projection of the gate of the transistor on the substrate is the active portion of the transistor, and an area of the semiconductor layer not overlapping with an orthographic projection of the transistor on the substrate is the source or the drain of the transistor.
13. 13 . The display substrate according to claim 12 , wherein the display substrate further comprises a sixth conductive layer, wherein the sixth conductive layer is located on a side of the semiconductor layer away from the fifth conductive layer; the sixth conductive layer comprises the first light emitting control signal line and the first reset signal line, wherein an orthographic projection of the first light emitting control signal line on the substrate overlaps with an orthographic projection of the first light emitting control auxiliary line on the substrate, and an orthographic projection of the first reset signal line on the substrate overlaps with an orthographic projection of the first reset auxiliary line on the substrate; in the area where the sub-pixel is located, the sixth conductive layer further comprises a first conductive portion, a third conductive portion, a fourth conductive portion, a fifth conductive portion, a sixth conductive portion and a seventh conductive portion, wherein the fifth conductive portion and the first light emitting control signal line are of an integrated structure, and the seventh conductive portion and the first reset signal line are of an integrated structure; and an orthographic projection of the first conductive portion on the substrate at least partially overlaps with the orthographic projection of the active portion of the first transistor on the substrate and the orthographic projection of the active portion of the second transistor on the substrate respectively, an orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the third transistor on the substrate, an orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the fourth transistor on the substrate, an orthographic projection of the fifth conductive portion on the substrate at least partially overlaps with the orthographic projection of the fifth transistor on the substrate, an orthographic projection of the sixth conductive portion on the substrate at least partially overlaps with the orthographic projection of the sixth transistor on the substrate, and an orthographic projection of the seventh conductive portion on the substrate at least partially overlaps with the orthographic projection of the seventh transistor on the substrate.
14. 14 . The display substrate according to claim 13 , wherein the transistor is a transistor with a double-gate structure, and the first conductive portion serves as another gate of the first transistor and the second transistor, the third conductive portion serves as another gate of the third transistor, the fourth conductive portion serves as another gate of the fourth transistor, the fifth conductive portion serves as another gate of the fifth transistor, the sixth conductive portion serves as another gate of the sixth transistor and the seventh conductive portion serves as another gate of the seventh transistor.
15. 15 . The display substrate according to claim 12 , wherein a material of the semiconductor layer comprises a metal oxide.
16. 16 . A display panel, comprising the display substrate according to claim 1 .

Description

CROSS-REFERENCE TO RELATED APPLICATION The present disclosure claims the priority of Chinese patent application filed on Feb. 24, 2023 before the CNIPA, China National Intellectual Property Administration with the application number of PCT/CN2023/078138, and the title of “PIXEL DRIVING CIRCUIT AND DRIVING METHOD, DISPLAY SUBSTRATE AND DISPLAY DEVICE”, and the priority of Chinese patent application filed on Apr. 26, 2023 before the CNIPA, China National Intellectual Property Administration with the application number of 202310463215.6, and the title of “DISPLAY SUBSTRATE AND DISPLAY PANEL”, the entire disclosures of the aforementioned two patent applications are hereby incorporated herein by reference. FIELD The present disclosure relates to the field of display technologies, and more particularly to a display substrate and a display panel. BACKGROUND Active matrix organic light emitting diode (AMOLED) panels are more and more widely used. Pixel display devices of the AMOLED are organic light emitting diodes (OLEDs), and the AMOLED can emit light by driving a thin film transistor to generate a driving current in a saturated state, and the driving current drives a light emitting device to emit light. SUMMARY Embodiments of the present disclosure adopt the following technical solutions. In a first aspect, the embodiments of the present disclosure provide a display substrate, including: a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein each of the plurality of sub-pixels includes a pixel driving circuit and a light emitting device that are electrically connected, and the pixel driving circuit includes: a driving module electrically connected to a first node, a second node and a third node respectively, wherein the third node is electrically connected to an anode of the light emitting device, and the driving module is configured to conduct a path between the second node and the anode under a control of a voltage of the first node, and generate a current in the path for driving the light emitting device to emit light;a first reset module and a second reset module, wherein the first reset module is electrically connected to the third node, a first reset signal line and a second initialization signal line respectively, and is configured to initialize a voltage of the anode under a control of a signal transmitted by the first reset signal line; and the second reset module is electrically connected to the first node, a fourth node, a second reset signal line and a first initialization signal line respectively, and is configured to initialize a voltage of the first node and a voltage of the fourth node under a control of a signal transmitted by the second reset signal line;an input module electrically connected to a scanning signal line, a data signal line and a fifth node respectively, and configured to input a data signal transmitted by the data signal line to the fifth node under a control of a signal input by the scanning signal line;a first light emitting control module and a second light emitting control module, wherein the first light emitting control module is electrically connected to a first light emitting control signal line, a positive power signal line and the second node respectively, and is configured to input a signal transmitted by the positive power signal line to the second node under a control of a signal transmitted by the first light emitting control signal line; and the second light emitting control module is electrically connected to the first node, the fifth node and a second light emitting control signal line respectively, and is configured to transmit a signal of the fifth node to the first node under a control of a signal transmitted by the second light emitting control signal line; anda compensation module electrically connected to the third node, the fourth node and the fifth node respectively, and configured to compensate a threshold voltage of the driving module,wherein the pixel driving circuit includes a plurality of transistors, and each of the plurality of transistors includes an active portion; the display substrate further includes a plurality of conductive patterns, a part of the plurality of conductive patterns are located on a side of the active portion of the transistor away from the substrate, and a part of the plurality of conductive patterns are located between the active portion of the transistor and the substrate, wherein orthographic projections of active portions of the plurality of transistors in at least one of the plurality of sub-pixels on the substrate are located within orthographic projections of the plurality of conductive patterns on the substrate. In at least one embodiment of the present disclosure, the plurality of conductive patterns include a combination of one or more of the anode of the light emitting device, a signal line, a connection wiring, and a gate of the transistor. In at least one embodiment of the present