US-12626659-B2 - Display device and method for driving display device

Abstract

The present disclosure relates to a display device, and more specifically, to a display device in which noise characteristics are improved by outputting mutually inverted switching signals from a first power integrated circuit (IC) and a second power IC. According to the present disclosure, the noise characteristics of the display device are improved by outputting the mutually inverted switching signals from the first power IC and the second power IC.

Inventors

• Jaekown Chae
• Donghwan Kim
• EunSup YOON

Assignees

• LG DISPLAY CO., LTD.

Dates

Publication Date

20260512

Application Date

20241022

Priority Date

20231228

Claims (17)

1. 1 . A display device, comprising: a timing controller configured to output image data, a command signal, and a data enable signal; a display panel including a plurality of pixels and data lines that are connected to the plurality of pixels; a first power driver configured to supply first power to the display panel, the first power driver including a first power integrated circuit (IC) configured to generate a first switching signal based on the data enable signal; a second power driver configured to supply second power to the display panel, the second power driver including a second power IC configured to generate a second switching signal based on the data enable signal, a frequency generator circuit configured to generate a clock signal and supply the clock signal to the first power IC; and a phase detector configured to receive the first switching signal from the first power IC and receive the second switching signal from the second power IC, wherein the first switching signal and the second switching signal have a same phase width, inverted shapes with respect to each other, and a same absolute value of magnitude, wherein the first power IC is configured to generate an inverted clock signal by inverting the clock signal, and supply the inverted clock signal to the second power IC, and wherein the phase detector includes: an edge detector circuit configured to detect first edges of the first switching signal and second edges of the second switching signal, and generate edge signals based on the first edges and the second edges; and an integrator configured to generate an accumulated signal by accumulating the edge signals and supply the accumulated signal to the first power IC.
2. 2 . The display device of claim 1 , wherein the data enable signal comprises a first data enable signal and a second data enable signal, and the timing controller is further configured to supply the first data enable signal to the first power IC, and supply the second data enable signal to the second power IC.
3. 3 . The display device of claim 1 , wherein the data enable signal comprises a first data enable signal and a second data enable signal, and the display device further comprising: a delay circuit configured to: receive the first data enable signal from the timing controller; generate a second data enable signal by delaying the first data enable signal; and supply the second data enable signal to the second power IC, wherein the timing controller is further configured to supply the first data enable signal to the first power IC.
4. 4 . The display device of claim 3 , wherein the delay circuit comprises: a resistor connected in series to a first signal line through which the first data enable signal is transmitted; and a capacitor connected between a second signal line through which the second data enable signal is transmitted and a ground line.
5. 5 . The display device of claim 1 , further comprising a frequency generator circuit configured to: generate a clock signal and an inverted clock signal; supply the clock signal to the first power IC; and supply the inverted clock signal to the second power IC.
6. 6 . The display device of claim 1 , further comprising: a frequency generator circuit configured to generate a clock signal and supply the clock signal to the first power IC; and an inverter configured to receive the clock signal from the frequency generator circuit and output an inverted clock signal of the received clock signal to the second power IC.
7. 7 . A method of driving a display device, comprising: outputting, by a timing controller of the display device, a data enable signal; generating, by a first power integrated circuit (IC) of a first power driver of the display device, a first switching signal based on the data enable signal; supplying, by the first power driver, first power to a display panel of the display device based on the first switching signal; generating, by a second power IC of a second power driver of the display device, a second switching signal based on the data enable signal; supplying, by the second power driver, second power to the display panel based on the second switching signal; generating and supplying, by a frequency generator circuit of the display device, a clock signal to the first power IC; and receiving, by a phase detector of the display device, the first switching signal from the first power IC and receive the second switching signal from the second power IC, wherein the first switching signal and the second switching signal have a same phase width, inverted shapes with respect to each other, and a same absolute value of magnitude, wherein the first power IC is configured to generate an inverted clock signal by inverting the clock signal, and supply the inverted clock signal to the second power IC, and wherein the phase detector includes: an edge detector circuit configured to detect first edges of the first switching signal and second edges of the second switching signal, and generate edge signals based on the first edges and the second edges; and an integrator configured to generate an accumulated signal by accumulating the edge signals and supply the accumulated signal to the first power IC.
8. 8 . The method of claim 7 , wherein the data enable signal comprises a first data enable signal and a second data enable signal, and the method further comprising: supplying, by the timing controller, the first data enable signal to the first power IC; and supplying, by the timing controller, the second data enable signal to the second power IC.
9. 9 . The method of claim 7 , the data enable signal comprises a first data enable signal and a second data enable signal, and the method further comprising: supplying, by the timing controller, the first data enable signal to the first power IC; receiving, by a delay circuit of the display device, the first data enable signal from the timing controller; generating, by the delay circuit, a second data enable signal by delaying the first data enable signal; and supplying, by the delay circuit, the second data enable signal to the second power IC.
10. 10 . The method of claim 7 , further comprising: generating, by a frequency generator circuit of the display device, a clock signal and an inverted clock signal; supplying, by the frequency generator circuit, the clock signal to the first power IC; and supplying, by the frequency generator circuit, the inverted clock signal to the second power IC.
11. 11 . The method of claim 7 , further comprising: generating, by a frequency generator circuit of the display device, a clock signal; supplying, by the frequency generator circuit, the clock signal to the first power IC; receiving, by an inverter of the display device, the clock signal; and outputting, by the inverter, an inverted clock signal of the received clock signal to the second power IC.
12. 12 . A display device, comprising: a timing controller configured to generate one or more data enable signals; a first display panel having a first plurality of pixels; a second display panel having a second plurality of pixels; a first power driver configured to generate a first switching signal having a first phase based on the one or more data enable signals and generate one or more first output voltages based on the first switching signal, wherein the one or more first output voltages include one or more first power supply voltages for supplying power to the first display panel; a second power driver configured to generate a second switching signal having a second phase that is different from the first phase based on the one or more data enable signals and generate one or more second output voltages based on the second switching signal, wherein the one or more second output voltages include one or more second power supply voltages for supplying power to the second display panel; a frequency generator circuit configured to generate a clock signal and supply the clock signal to the first power driver; and a phase detector configured to receive the first switching signal from the first power driver and receive the second switching signal from the second power driver, wherein the first power driver is configured to generate an inverted clock signal by inverting the clock signal, and supply the inverted clock signal to the second power driver, and wherein the phase detector includes: an edge detector circuit configured to detect first edges of the first switching signal and second edges of the second switching signal, and generate edge signals based on the first edges and the second edges; and an integrator configured to generate an accumulated signal by accumulating the edge signals and supply the accumulated signal to the first power driver.
13. 13 . The display device of claim 12 , wherein the first phase is opposite to the second phase, and the first switching signal and the second switching signal have a same cycle of one horizontal period and a same absolute value of magnitude.
14. 14 . The display device of claim 12 , wherein: the one or more data enable signals include a first data enable signal; the display device further comprises a delay circuit configured to receive the first data enable signal and generate a second data enable signal by delaying the first data enable signal; the first power driver is further configured to generate, based on the first data enable signal, the first switching signal having the first phase; and the second power driver is further configured to generate, based on the second data enable signal, the second switching signal having the second phase.
15. 15 . The display device of claim 12 , wherein: the one or more data enable signals include a clock signal; the timing controller comprises a frequency generator circuit configured to generate the clock signal; the display device further comprises an inverter configured to receive the clock signal and output an inverted clock signal; the first power driver is further configured to generate, based on the clock signal, the first switching signal having the first phase; and the second power driver is further configured to generate, based on the inverted clock signal, the second switching signal having the second phase.
16. 16 . The display device of claim 12 , wherein: the one or more data enable signals include a clock signal; the timing controller includes a frequency generator circuit configured to generate the clock signal; the first power driver includes a first power integrated circuit (IC) configured to: receive the clock signal from the frequency generator circuit, generate, based on the clock signal, the first switching signal having the first phase, and generate an inverted clock signal by inverting the clock signal; and the second power driver includes a second power IC configured to: receive the inverted clock signal from the first power IC, and generate, based on the inverted clock signal, the second switching signal having the second phase.
17. 17 . The display device of claim 12 , further comprising: a first gate driver circuit connected to the first plurality of pixels; and a second gate driver circuit connected to the second plurality of pixels, wherein the first power driver is further configured to generate at least one first output voltage based on the first switching signal and supply the at least one first output voltage to the first gate driver circuit, and wherein the second power driver is further configured to generate at least one second output voltage based on the second switching signal and supply the at least one second output voltage to the second gate driver circuit.

Description

CROSS REFERENCE TO RELATED APPLICATION The present application claims the priority from Republic of Korea Patent Application No. 10-2023-0195428, filed on Dec. 28, 2023, which is hereby incorporated by reference in its entirety. BACKGROUND Field The present disclosure relates to a display device, and more specifically, to a display device in which noise characteristics are improved by outputting an inverted switching signal from a first power integrated circuit (IC) and a second power IC. Description of Related Art Recently, as the information age enters, a display field in which electrical information signals are visually expressed has developed rapidly, and in response thereto, various display devices having excellent performance, such as thinness, lightness, and low power consumption, are being developed. Examples of display devices may include a liquid crystal display (LCD) device, an organic light emitting diode (OLED) display device, a quantum dot display device, etc. Such a display device uses a timing controller, a frequency generator, a power driver, etc. for an operation thereof. SUMMARY The present disclosure is directed to providing a display device in which noise characteristics are improved by outputting an inverted switching signal from a first power integrated circuit (IC) and a second power IC of the display device. A display device according to one embodiment may include a timing controller configured to output image data, a command signal, and a data enable signal, a display panel including a plurality of pixels and data lines that are connected to the plurality of pixels, a first power driver configured to supply first power to the display panel, the first power driver including a first power integrated circuit (IC) configured to generate a first switching signal based on the data enable signal, and a second power driver configured to supply second power to the display panel, the second power driver including a second power IC configured to generate a second switching signal based on the data enable signal, wherein the first switching signal and the second switching signal have a same phase width with respect to each other, inverted shapes, and a same absolute value of magnitude. The data enable signal may include a first data enable signal and a second data enable signal. The timing controller may supply the first data enable signal to the first power IC, and supply the second data enable signal to the second power IC. The data enable signal may include a first data enable signal. The display device may further include a delay circuit configured to receive the first data enable signal from the timing controller, generate a second data enable signal by delaying the first data enable signal, and supply the second data enable signal to the second power IC, wherein the timing controller may supply the first data enable signal to the first power IC. The delay circuit may include a resistor connected in series to a first signal line through which the first data enable signal is transmitted, and a capacitor connected between a second signal line through which the second data enable signal is transmitted and a ground line. The display device may further include a frequency generator circuit configured to generate a clock signal and an inverted clock signal, supply the clock signal to the first power IC, and supply the inverted clock signal to the second power IC. The display device may further include a frequency generator circuit configured to generate a clock signal and supply the clock signal to the first power IC, and an inverter configured to receive the clock signal from the frequency generator and output an inverted clock signal of the received clock signal to the second power IC. The display device may further include a frequency generator circuit configured to generate a clock signal and supply the clock signal to the first power IC, wherein the first power IC may generate an inverted clock signal by inverting the clock signal, and supply the inverted clock signal to the second power IC. The display device may further include a phase detector configured to receive the first switching signal from the first power IC and receive the second switching signal from the second power IC. The phase detector may include an edge detector circuit configured to detect first edges of the first switching signal and second edges of the second switching signal, and generate edge signals based on the first edges and the second edges, and an integrator configured to generate an accumulated signal by accumulating the edge signals and supply the accumulated signal to the first power IC. A method of driving a display device may include outputting, by a timing controller of the display device, a data enable signal, generating, by a first power IC of a power driver of the display device, first a switching signal based on the data enable signal, supplying, by the first power driver, first power to a display pan