US-12626663-B2 - Pixel, display device having the same, and electronic device having the same

Abstract

Provided are a pixel and a display device having the same. The pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, a third capacitor, and a light-emitting element.

Inventors

• Jiyoung Lee
• Hyunyoung Choi
• Sang-Gu Lee
• Yongwoo Lee
• HYUNG UK CHO
• Jisong Chae

Assignees

• SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date

20260512

Application Date

20250317

Priority Date

20240715

Claims (20)

1. 1 . A pixel comprising: a first transistor comprising a gate electrode connected to a first node, a first electrode configured to receive a first power voltage, and a second electrode connected to a second node; a second transistor comprising a gate electrode configured to receive a first gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a third transistor comprising a gate electrode configured to receive a second gate signal, a first electrode connected to a third node, and a second electrode configured to receive a second power voltage; a fourth transistor comprising a gate electrode configured to receive a third gate signal, a first electrode connected to the first node, and a second electrode configured to receive a third power voltage; a fifth transistor comprising a gate electrode configured to receive a fourth gate signal, a first electrode configured to receive the third power voltage, and a second electrode connected to a fourth node; a sixth transistor comprising a gate electrode configured to receive a fifth gate signal, a first electrode configured to receive the first power voltage, and a second electrode connected to the fourth node; a seventh transistor comprising a gate electrode connected to the fourth node, a first electrode connected to the second node, and a second electrode connected to the third node; a first capacitor comprising a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor comprising a first electrode connected to the second node and a second electrode configured to receive the second gate signal; a third capacitor comprising a first electrode connected to the fourth node and a second electrode configured to receive the second gate signal; and a light-emitting element comprising a first electrode connected to the third node and a second electrode configured to receive the second power voltage.
2. 2 . The pixel of claim 1 , wherein the third transistor comprises the second electrode configured to receive an initialization voltage.
3. 3 . The pixel of claim 1 , further comprising an eighth transistor comprising a gate electrode configured to receive an emission control signal, a first electrode configured to receive the first power voltage, and a second electrode connected to a fifth node, wherein the first electrode of the first transistor is connected to the fifth node.
4. 4 . The pixel of claim 1 , further comprising an eighth transistor comprising a gate electrode configured to receive an emission control signal, a first electrode connected to the second node, and a second electrode connected to a fifth node, wherein the first electrode of the seventh transistor is connected to the fifth node.
5. 5 . The pixel of claim 1 , further comprising an eighth transistor comprising a gate electrode configured to receive an emission control signal, a first electrode connected to the second node, and a second electrode connected to a fifth node, wherein the second electrode of the first capacitor is connected to the fifth node.
6. 6 . The pixel of claim 1 , wherein the second gate signal and the fifth gate signal change from a first signal to a second signal, and when the third gate signal is the first signal, a threshold voltage of the first transistor is compensated.
7. 7 . The pixel of claim 6 , wherein based on the first transistor being turned on, a voltage that the fourth transistor applies to the gate electrode of the first transistor is equal to a sum of a voltage applied to the second electrode of the first transistor and the threshold voltage of the first transistor.
8. 8 . The pixel of claim 1 , wherein a completely compensated threshold voltage is maintained for the first transistor based on the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor being turned off, based on each of the first gate signal, the second gate signal, the third gate signal, the fourth gate signal, and the fifth gate signal being a second signal.
9. 9 . The pixel of claim 1 , wherein the second gate signal, the third gate signal, and the fourth gate signal are each a first signal in a same length of period.
10. 10 . The pixel of claim 9 , wherein the fifth gate signal and the second gate signal are each the first signal in a same length of period.
11. 11 . A display device comprising: a scan driver configured to transmit a plurality of scan signals to a plurality of scan lines; a data driver configured to transmit a plurality of data signals to a plurality of data lines; a display unit comprising a plurality of pixels each connected to a corresponding scan line among the plurality of scan lines and a corresponding data line among the plurality of data lines, wherein the plurality of pixels are configured to emit light, respectively, according to corresponding data signals to display an image; and a controller configured to control the scan driver and the data driver, to generate the plurality of data signals, and to apply the generated plurality of data signals to the data driver, wherein each of the plurality of pixels comprises: a first transistor comprising a gate electrode connected to a first node, a first electrode configured to receive a first power voltage, and a second electrode connected to a second node; a second transistor comprising a gate electrode configured to receive a first gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a third transistor comprising a gate electrode configured to receive a second gate signal, a first electrode connected to a third node, and a second electrode configured to receive a second power voltage; a fourth transistor comprising a gate electrode configured to receive a third gate signal, a first electrode connected to the first node, and a second electrode configured to receive a third power voltage; a fifth transistor comprising a gate electrode configured to receive a fourth gate signal, a first electrode configured to receive the third power voltage, and a second electrode connected to a fourth node; a sixth transistor comprising a gate electrode configured to receive a fifth gate signal, a first electrode configured to receive the first power voltage, and a second electrode connected to the fourth node; a seventh transistor comprising a gate electrode connected to the fourth node, a first electrode connected to the second node, and a second electrode connected to the third node; a first capacitor comprising a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor comprising a first electrode connected to the second node and a second electrode configured to receive the second gate signal; a third capacitor comprising a first electrode connected to the fourth node and a second electrode configured to receive the second gate signal; and a light-emitting element comprising a first electrode connected to the third node and a second electrode configured to receive the second power voltage.
12. 12 . The display device of claim 11 , wherein the third transistor comprises the second electrode configured to receive an initialization voltage.
13. 13 . The display device of claim 11 , wherein each of the plurality of pixels further comprises an eighth transistor that comprises a gate electrode configured to receive an emission control signal, a first electrode configured to receive the first power voltage, and a second electrode connected to a fifth node, and the first electrode of the first transistor is connected to the fifth node.
14. 14 . The display device of claim 11 , wherein each of the plurality of pixels further comprises an eighth transistor that comprises a gate electrode configured to receive an emission control signal, a first electrode connected to the second node, and a second electrode connected to a fifth node, and the first electrode of the seventh transistor is connected to the fifth node.
15. 15 . The display device of claim 11 , wherein each of the plurality of pixels further comprises an eighth transistor comprising a gate electrode configured to receive an emission control signal, a first electrode connected to the second node, and a second electrode connected to a fifth node, and the second electrode of the first capacitor is connected to the fifth node.
16. 16 . The display device of claim 11 , wherein the second gate signal and the fifth gate signal change from a first signal to a second signal, and when the third gate signal is the first signal, a threshold voltage of the first transistor is compensated.
17. 17 . The display device of claim 16 , wherein based on the first transistor being turned on, a voltage that the fourth transistor applies to the gate electrode of the first transistor is equal to a sum of a voltage applied to the second electrode of the first transistor and the threshold voltage of the first transistor.
18. 18 . The display device of claim 11 , wherein a completely compensated threshold voltage is maintained for the first transistor based on the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor being turned off, based on each of the first gate signal, the second gate signal, the third gate signal, the fourth gate signal, and the fifth gate signal being a second signal.
19. 19 . The display device of claim 11 , wherein the second gate signal, the third gate signal, and the fourth gate signal are each a first signal in a same length of period, and the fifth gate signal and the second gate signal are each the first signal in a same length of period.
20. 20 . An electronic device, comprising the display device of claim 11 .

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to and the benefit of Korean Patent Application No. 10-2024-0093262, filed on Jul. 15, 2024 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. BACKGROUND 1. Field Aspects of some embodiments of the present disclosure relate to a pixel, a display device having the same, and an electronic device having the same. 2. Description of the Related Art A pixel emits light based on a data voltage and includes a transistor (e.g., a thin film transistor; TFT) that controls driving of the pixel. A display device (particularly, an organic light emitting display device) may display images in a progressive emission method in which rows of pixels emit light sequentially, or in a simultaneous emission method in which all pixels emit light simultaneously after sequential data writing is completed. In order to improve defective displays, such as luminance deviation between pixels, and the like, a display device driven by the simultaneous emission method may further include components inside a pixel to compensate for a threshold voltage of a driving transistor, initialize an anode of an organic light emitting diode, etc. However, when the components for the threshold voltage compensation and the initialization are added, lines and transistors are also added, which causes an increase in pixel size and a difficulty in implementing high resolution. Accordingly, because a plurality of pixels must be integrated within a narrow area in a high-resolution display device, there is a need to develop a high-density pixel and a display device including the same. The aforementioned background technology is technical information possessed by the inventor for derivation of the present disclosure or acquired by the inventor during the derivation of the present disclosure, and is not necessarily prior art disclosed to the public before the application of the present disclosure. The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art. SUMMARY Some embodiments according to the present disclosure include a pixel and a display device including the same. The characteristics of embodiments according to the present disclosure are not limited to the characteristics described above, and other aspects and characteristics of embodiments according to the present disclosure will be understood by the following description and will be more apparent from the embodiments of the present disclosure. Further, it will be readily understood that the aspects and characteristics of embodiments according to the present disclosure can be realized by the characteristics set forth in the appended claims and combinations thereof. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments. According to some embodiments, a pixel includes a first transistor that includes a gate electrode connected to a first node, a first electrode to receive a first power voltage, and a second electrode connected to a second node; a second transistor that includes a gate electrode to receive a first gate signal, a first electrode to receive a data voltage, and a second electrode connected to the first node; a third transistor that includes a gate electrode to receive a second gate signal, a first electrode connected to a third node, and a second electrode to receive a second power voltage; a fourth transistor that includes a gate electrode to receive a third gate signal, a first electrode connected to the first node, and a second electrode to receive a third power voltage; a fifth transistor that includes a gate electrode to receive a fourth gate signal, a first electrode to receive the third power voltage, and a second electrode connected to a fourth node; a sixth transistor that includes a gate electrode to receive a fifth gate signal, a first electrode to receive the first power voltage, and a second electrode connected to the fourth node; a seventh transistor that includes a gate electrode connected to the fourth node, a first electrode connected to the second node, and a second electrode connected to the third node; a first capacitor that includes a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor that includes a first electrode connected to the second node and a second electrode to receive the second gate signal; a third capacitor that includes a first electrode connected to the fourth node and a second electrode to receive the second gate signal; and a light-emitting element that includes a first electrode connected to the third node and a second electrode to receive the second power v